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| preliminary fme-mb96390 rev 3 fujitsu semiconductor data sheet copyright ?2010 fujitsu semiconductor limited all rights reserved 2010.6 for the information for microcontroller supports, see the following web site. this web site includes the "customer design review supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ 16-bit proprietary microcontroller cmos f 2 mc-16fx mb96390 series mb96f395 *1 description mb96390 series is based on fujitsu s advanced 16fx architecture (16-bit with instruction pipeline for risc-like performance). the cpu uses the same instruction set as the established 16lx series - thus allowing for easy migration of 16lx software to the new 16fx products. 16fx improvements compared to the previous generation include signi?antly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. for highest processing speed at optimized power consumption an internal pll can be selected to supply the cpu with up to 40mhz operation frequency from an external 4mhz resonator. the result is a minimum instruction cycle time of 25ns going together with excellent emi behavior. an on-chip clock modulation circuit signi?antly reduces emission peaks in the frequency spectrum. the emitted power is minimized by the on-chip voltage regulator that reduces the internal cpu voltage. a ?xible clock tree allows to select suitable operation frequencies for peripheral resources independent of the cpu speed. *1: these devices are under development and speci?ation is preliminary. these products under development may change its speci?ation without notice. note: f 2 mc is the abbreviation of fujitsu flexible microcontroller
preliminary mb96390 series 2 fme-mb96390 rev 3 features feature description technology 0.18 m cmos cpu ? 2 mc-16fx cpu up to 40 mhz internal, 25 ns instruction cycle time optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) 8-byte instruction execution queue signed multiply (16-bit 16-bit) and divide (32-bit/16-bit) instructions available system clock on-chip pll clock multiplier (x1 - x25, x1 when pll stop) 3 mhz - 16 mhz external crystal oscillator clock (maximum frequency when using ceramic resonator depends on q-factor). up to 40 mhz external clock 32-100 khz subsystem quartz clock 100khz/2mhz internal rc clock for quick and safe startup, oscillator stop detection, watchdog clock source selectable from main- and subclock oscillator (part number suffix ?? and on-chip rc oscillator, independently for cpu and 2 clock domains of peripherals. low power consumption - 13 operating modes : (different run, sleep, timer modes, stop mode) clock modulator on-chip voltage regula- tor internal voltage regulator supports reduced internal mcu voltage, offering low emi and low power consumption figures low voltage reset reset is generated when supply voltage is below minimum. code security protects rom content from unintended read-out memory patch function replaces rom content can also be used to implement embedded debug support interrupts fast interrupt processing 8 programmable priority levels non-maskable interrupt (nmi) timers three independent clock timers (23-bit rc clock timer, 23-bit main clock timer, 17-bit sub clock timer) watchdog timer preliminary mb96390 series fme-mb96390 rev 3 3 can supports can protocol version 2.0 part a and b iso16845 certified bit rates up to 1 mbit/s 32 message objects each message object has its own identifier mask programmable fifo mode (concatenation of message objects) maskable interrupt disabled automatic retransmission mode for time triggered can applications programmable loop-back mode for self-test operation usart full duplex usarts (sci/lin) wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c up to 400 kbps master and slave functionality, 7-bit and 10-bit addressing a/d converter sar-type 10-bit resolution signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer reload timers 16-bit wide prescaler with 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 of peripheral clock frequency event count function free running timers signals an interrupt on overflow, supports timer clear upon match with output compare (0, 4), prescaler with 1, 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 , 1/2 7 ,1/2 8 of peripheral clock frequency input capture units 16-bit wide signals an interrupt upon external event rising edge, falling edge or rising & falling edge sensitive output compare units 16-bit wide signals an interrupt when a match with 16-bit i/o timer occurs a pair of compare registers can be used to generate an output signal. programmable pulse generator 16-bit down counter, cycle and duty setting registers interrupt at trigger, counter borrow and/or duty match pwm operation and one-shot operation internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and reload timer underflow as clock input can be triggered by software or reload timer feature description preliminary mb96390 series 4 fme-mb96390 rev 3 stepper motor control- ler stepper motor controller with integrated high current output drivers four high current outputs for each channel two synchronized 8/10-bit pwms per channel internal prescaling for pwm clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral clock separate power supply for high current output drivers lcd controller lcd controller with up to 4 com seg internal or external voltage generation duty cycle: selectable from options: 1/2, 1/3 and 1/4 fixed 1/3 bias programmable frame period clock source selectable from three options (peripheral clock, subclock or rc oscillator clock) on-chip drivers for internal divider resistors or external divider resistors on-chip data memory for display lcd display can be operated in timer mode blank display: selectable all seg, com and v pins can be switched between general and specialized purposes external divided resistors can be also used to shut off the current when lcd is deactivated sound generator 8-bit pwm signal is mixed with tone frequency from 16-bit reload counter pwm clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral clock real time clock can be clocked either from sub oscillator (devices with part number suffix ??, main oscillator or from the rc oscillator facility to correct oscillation deviation of sub clock or rc oscillator clock (clock calibration) read/write accessible second/minute/hour registers can signal interrupts every half second/second/minute/hour/day internal clock divider and prescaler provide exact 1s clock external interrupts edge sensitive or level sensitive interrupt mask and pending bit per channel each available can channel rx has an external interrupt for wake-up selected usart channels sin have an external interrupt for wake-up non maskable interrupt disabled after reset once enabled, can not be disabled other than by reset. level high or level low sensitive pin shared with external interrupt 0. feature description preliminary mb96390 series fme-mb96390 rev 3 5 alarm comparator monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined thresholds threshold voltages defined externally or generated internally status is readable, interrupts can be masked separately i/o ports virtually all external pins can be used as general purpose i/o all push-pull outputs (except when used as i2c sda/scl line) bit-wise programmable as input/output or peripheral signal bit-wise programmable input enable bit-wise programmable input levels: automotive / cmos-schmitt trigger / ttl bit-wise programmable pull-up resistor bit-wise programmable output driving strength for emi optimization packages 100-pin plastic lqfp flash memory supports automatic programming, embedded algorithm write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycles: 10,000 times data retention time: 20 years erase can be performed on each sector individually sector protection flash security feature to protect the content of the flash low voltage detection during flash erase feature description preliminary mb96390 series 6 fme-mb96390 rev 3 product lineup features mb96v300b mb96(f)39x product type evaluation sample flash product: mb96f39x mask rom product: mb9639x product options ys na low voltage reset persistently on / single clock devices rs low voltage reset can be disabled / single clock devices yw low voltage reset persistently on / dual clock devices rw low voltage reset can be disabled / dual clock devices flash/rom ram 160kb 5kb rom/flash memory emulation by external ram, 92kb internal ram mb96f395y *1 , mb96f395r *1 , package bga416 fpt-100p-m20 dma 16 channels 0 channels usart 10 channels 3 channels i2c 2 channels 1 channel a/d converter 40 channels 11 channels a/d converter reference voltage switch yes no 16-bit reload timer 6 channels + 1 channel (for ppg) 4 channels + 1 channel (for ppg) 16-bit free-running timer 4 channels 2 channels 16-bit output compare 12 channels 4 channels 16-bit input capture 12 channels 4 channels 16-bit programmable pulse generator 20 channels 4 channels can interface 5 channels 1 channels stepping motor controller 6 channels 4 channels external interrupts 16 channels 8 channels non-maskable interrupt 1 channel sound generator 2 channels 1 channels lcd controller 4 com x 72 seg 4 com x 49 seg real time clock 1 preliminary mb96390 series fme-mb96390 rev 3 7 *1: these devices are under development and speci?ation is preliminary. these products under development may change its speci?ation without notice. i/o ports 136 74 for part number with suf? "w", 76 for part number with suf? "s" alarm comparator 2 channels 1 channels external bus interface yes no clock output function 2 channels low voltage reset yes on-chip rc-oscillator yes features mb96v300b mb96(f)39x preliminary mb96390 series 8 fme-mb96390 rev 3 block diagrams block diagram of mb96f39x 4 ch. pwm1m0 ... pwm1m2,pwm1m4 pwm1p0 ... pwm1p2,pwm1p4 pwm2m0 ... pwm2m2,pwm2m4 pwm2p0 ... pwm2p2,pwm2p4 dv cc dv ss boot rom peripheral bus bridge peripheral bus bridge 16fx core bus (clkb) usart 3 ch. 10-bit adc 11 ch. alarm comparator 1 ch. can interface 1 ch. external interrupt sound generator lcd driver real time clock controller/ watchdog ram voltage regulator sin0...sin2 sot0...sot2 sck0...sck2 wot sgo0 sga0 av cc av ss avrh avrl an2,3,4,6,7,8,10 adtg frck0 frck0_r int0 ... int7 v0 ... v3 com0 ... com3 seg0 ... seg64 tx0 rx0 peripheral bus 1 (clkp1) peripheral bus 2 (clkp2) v cc v ss c stepper motor controller i/o timer 1 icu 6/7 frck1 in6,in7 1 ch. 16fx cpu interrupt controller clock & mode controller flash memory a memory patch unit nmi ckot0_r, ckot1, ckot1_r ckotx0, ckotx1, ckotx1_r x0, x1 x0a, x1a *1 rstx md0...md2 i2c 1 ch. sda0 scl0 16-bit reload timer 4 ch. tin0, tin1 tin2, tin3 tot0, tot1 tot2, tot3 i/o timer 0 icu 0/1 ocu 0/1/2/3 in0 in0_r,in1_r out0 ... out3 out0_r,out2_r int1_r ... int7_r in7_r 16-bit ppg 4 ch. rlt6 ppg0,ppg1,ppg3 ttg0,ttg2,ttg3 ppg0_r ... ppg3_r alarm0 (except 5,6,8,9,10, 29,31,32,34,35,48 an11,12,14,15 49,50,54,58,62) *1: x0a, x1a only available on devices with suf? ? preliminary mb96390 series fme-mb96390 rev 3 9 pin assignments pin assignment of mb96f39x lqfp - 100 package code (mold) fpt-100p-m20 (fpt-100p-m20) 89 12345 7 6 101112131415161718192021222324 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 76 77 78 79 vss p00_3/int6_r/seg15 p00_4/int7_r/seg16 p00_5/ttg2/in6/seg17 p00_6/ttg3/in7/seg18 p00_7/sgo0/seg19 p01_0/sga0/seg20 p01_1/out0/ckot1/seg21 p01_2/out1/ckotx1/seg22 p01_3/seg23 p01_4/seg24 p01_5/seg25 p01_6/seg26 p01_7/ckotx1_r/seg27 p02_0/ckot1_r/seg28 p02_2/ckot0_r/in7_r/seg30 p02_5/out0_r/seg33 p03_0/v0/seg36 p03_1/v1/seg37 p03_2/v2/seg38 p03_3/v3/seg39 p03_4/int4/rx0 p03_5/tx0 p03_6/nmi/int0 vcc vss c p03_7/int1/sin1/seg40 p13_0/int2/sot1/seg41 p13_1/int3/sck1/seg42 p13_2/ppg0/tin0/frck1/seg43 p13_3/ppg1/tot0/wot/seg44 p13_4/sin0/int6/seg45 p13_5/sot0/adtg/int7/seg46 p13_6/sck0/ckotx0/seg47 p04_4/ppg3/sda0 p04_5/scl0 p06_2/an2/int5/seg51 p06_3/an3/frck0/seg52 p06_4/an4/in0/ttg0/seg53 p06_6/an6/tin1/seg55 p06_7/an7/tot1/seg56 avcc avrh avrl avss p05_0/an8/alarm0/seg57 p05_2/an10/out2/seg59 p05_3/an11/out3/seg60 vcc vcc p10_3/pwm2m4 p10_2/pwm2p4/sck2 p10_1/pwm1m4/sot2/tot3 p10_0/pwm1p4/sin2/tin3 dvss dvcc p09_3/pwm2m2 p09_2/pwm2p2 p09_1/pwm1m2 p09_0/pwm1p2 p08_7/pwm2m1 p08_6/pwm2p1 p08_5/pwm1m1 dvss dvcc p08_4/pwm1p1 p08_3/pwm2m0 p08_2/pwm2p0 p08_1/pwm1m0 p08_0/pwm1p0 p05_7/an15/tot2/seg64 p05_6/an14/tin2/seg63 vss vcc p00_2/int5_r/seg14 p00_1/int4_r/seg13 p00_0/int3_r/seg12 p12_7/int1_r/seg11 p12_3/out2_r/seg7 p12_0/in1_r/seg4 p11_7/in0_r/seg3 p11_6/frck0_r/seg2 p11_5/seg1 p11_4/ppg3_r/seg0 p11_3/ppg2_r/com3 p11_2/ppg1_r/com2 p11_1/ppg0_r/com1 p11_0/com0 rstx x1a/p04_1 *1 x0a/p04_0 *1 vss x1 x0 md2 md1 md0 vss *1: devices with suf? w: x0a, x1a devices with suf? s: p04_0, p04_1 p05_4/an12/int2_r/seg61 preliminary mb96390 series 10 fme-mb96390 rev 3 pin function description pin function description (1 of 2) pin name feature description adtg adc a/d converter trigger input alarmn alarm comparator alarm comparator n input ann adc a/d converter channel n input av cc supply analog circuits power supply avrh adc a/d converter high reference voltage input avrl adc a/d converter low reference voltage input av ss supply analog circuits power supply c voltage regulator internally regulated power supply stabilization capacitor pin ckotn clock output function clock output function n output ckotn_r clock output function relocated clock output function n output ckotxn clock output function clock output function n inverted output ckotxn_r clock output function relocated clock output function n inverted output comn lcd lcd com pins dv cc supply smc pins power supply frckn free running timer free running timer n input frckn_r free running timer relocated free running timer n input inn icu input capture unit n input inn_r icu relocated input capture unit n input intn external interrupt external interrupt n input intn_r external interrupt relocated external interrupt n input mdn core input pins for specifying the operating mode. nmi external interrupt non-maskable interrupt input outn ocu output compare unit n waveform output outn_r ocu relocated output compare unit n waveform output pxx_n gpio general purpose io ppgn ppg programmable pulse generator n output ppgn_r ppg relocated programmable pulse generator n output pwmn smc smc pwm high current rstx core reset input preliminary mb96390 series fme-mb96390 rev 3 11 rxn can can interface n rx input sckn usart usart n serial clock input/output scln i2c i2c interface n clock i/o input/output sdan i2c i2c interface n serial data i/o input/output segn lcd lcd segment n sga sound generator sg amplitude output sgo sound generator sg sound/tone output sinn usart usart n serial data input sotn usart usart n serial data output tinn reload timer reload timer n event input totn reload timer reload timer n output ttgn ppg programmable pulse generator n trigger input txn can can interface n tx output vn lcd lcd voltage references v cc supply power supply v ss supply power supply wot rtc real timer clock output x0 clock oscillator input x0a clock subclock oscillator input (only for devices with suf? "w") x1 clock oscillator output x1a clock subclock oscillator output (only for devices with suf? "w") pin function description (2 of 2) pin name feature description preliminary mb96390 series 12 fme-mb96390 rev 3 pin circuit type pin circuit types (1 of 2) fpt-100p-m20 pin no. circuit type *1 1 supply 2f 3 to 10 j 11,12 n 13 to 17 k 18 supply 19 to 20 g 21 supply 22 to 24 k 25,26 supply 27 to 29 k 30 to 34 m 35,36 supply 37 to 43 m 44,45 supply 46 to 49 m 50, 51 supply 52 to 54 c 55, 56 a 57 supply 58,59 b *2 ) 58,59 h *3 60 e 61 to 74 j 75 to 76 supply 77 to 92 j 93 to 96 l preliminary mb96390 series fme-mb96390 rev 3 13 *1: please refer to i/o circuit type?for details on the i/o circuit types *2: devices with suf? ? *3: devices without suf? ? 97 to 99 h 100 supply pin circuit types (2 of 2) fpt-100p-m20 pin no. circuit type *1 preliminary mb96390 series 14 fme-mb96390 rev 3 i/o circuit type type circuit remarks a high-speed oscillation circuit: programmable between oscillation mode (ex- ternal crystal or resonator connected to x0/x1 pins) and fast external clock input (fci) mode (external clock connected to x0 pin) programmable feedback resistor = approx. 2 * 0.5 m ? . feedback resistor is grounded in the center when the oscillator is disabled or in fci mode b low-speed oscillation circuit: programmable feedback resistor = approx. 2*5m ? . feedback resistor is grounded in the center when the oscillator is disabled c mask rom and eva device: cmos hysteresis input pin flash device: cmos input pin e cmos hysteresis input pin pull-up resistor value: approx. 50 k ? x1 x0 r r mrfbe xout fci 0 1 fci or osc disable x1a x0a r r srfbe xout osc disable r hysteresis inputs r pull-up resistor hysteresis inputs preliminary mb96390 series fme-mb96390 rev 3 15 f power supply input protection circuit g a/d converter ref+ (avrh/avrh2) power sup- ply input pin with protection circuit flash devices do not have a protection circuit against vcc for pins avrh/avrh2 devices without avrh reference switch do not have an analog switch for the avrl pin h cmos level output (programmable i ol =5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. type circuit remarks ane avr ane pout pull-up control nout r hysteresis input automotive input ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown preliminary mb96390 series 16 fme-mb96390 rev 3 j cmos level output (programmable i ol =5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. seg or com output k cmos level output (programmable i ol =5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function. programmable pull-up resistor: 50k ? approx. analog input seg output type circuit remarks pout pull-up control nout r hysteresis input automotive input ttl input hysteresis input seg, com output standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown pout pull-up control nout r hysteresis input automotive input ttl input hysteresis input seg output analog input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown preliminary mb96390 series fme-mb96390 rev 3 17 l cmos level output (programmable i ol =5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. analog input vx input seg output m cmos level output (programmable i ol =5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma, i ol = 30ma, i oh = -30ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. type circuit remarks standby control for input shutdown pout pull-up control nout r hysteresis input hysteresis input seg output analog input standby control for input shutdown standby control for input shutdown standby control for input shutdown vx input ttl input automotive input pout pull-up control nout r hysteresis input automotive input ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown preliminary mb96390 series 18 fme-mb96390 rev 3 n cmos level output (i ol = 3ma, i oh = -3ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. *1: n-channel transistor has slew rate control ac- cording to i 2 c spec, irrespective of usage type circuit remarks pout pull-up control nout *1 r hysteresis input automotive input ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown preliminary mb96390 series fme-mb96390 rev 3 19 memory map mb96v300b mb96f39x ff:ffff h emulation rom user rom / reserved *4 de:0000 h external bus reserved 10:0000 h 0f:e000 h boot-rom boot-rom reserved reserved 0e:0000 h external ram 02:0000 h internal ram bank 1 01:0000 h rom/ram mirror rom/ram mirror 00:8000 h internal ram bank 0 internal ram bank 0 ramstart0 *2 reserved ramstart0 *3 00:0c00 h external bus peripherals peripherals 00:0380 h 00:0180 h gpr *1 gpr *1 00:0100 h dma reserved 00:00f0 h external bus reserved 00:0000 h peripheral peripheral *1: unused gpr banks can be used as ram area *2: for ramstart0 addresses, please refer to the table on the next page. *3: for eva device, ramstart0 depends on the con?uration of the emulated device. *4: for details about user rom area, see the user rom memory map for flash devices on the following pages. the dma area is only available if the device contains the corresponding resource. the available ram and rom area depends on the device. preliminary mb96390 series 20 fme-mb96390 rev 3 ramstart/end and external bus end addresses devices bank 0 ram size ramstart0 mb96f395 5kbyte 00:6e40 h preliminary mb96390 series fme-mb96390 rev 3 21 user rom memory map for flash devices mb96f395r mb96f395y alternative mode cpu address flash memory mode address flash size 160kbyte ff:ffff h ff:0000 h 3f:ffff h 3f:0000 h s39 - 64k fe:ffff h fe:0000 h 3e:ffff h 3e:0000 h s38 - 64k fd:ffff h fd:0000 h 3d:ffff h 3d:0000 h reserved fc:ffff h fc:0000 h 3c:ffff h 3c:0000 h fb:ffff h fb:0000 h 3b:ffff h 3b:0000 h fa:ffff h fa:0000 h 3a:ffff h 3a:0000 h f9:ffff h f9:0000 h 39:ffff h 39:0000 h f8:ffff h f8:0000 h 38:ffff h 38:0000 h f7:ffff h f7:0000 h 37:ffff h 37:0000 h f6:ffff h f6:0000 h 36:ffff h 36:0000 h f5:ffff h f5:0000 h 35:ffff h 35:0000 h f4:ffff h f4:0000 h 34:ffff h 34:0000 h f3:ffff h f3:0000 h 33:ffff h 33:0000 h f2:ffff h f2:0000 h 32:ffff h 32:0000 h f1:ffff h f1:0000 h 31:ffff h 31:0000 h f0:ffff h f0:0000 h 30:ffff h 30:0000 h e0:ffff h e0:0000 h df:ffff h df:8000 h df:7fff h df:6000 h 1f:7fff h 1f:6000 h sa3 - 8k df:5fff h df:4000 h 1f:5fff h 1f:4000 h sa2 - 8k df:3fff h df:2000 h 1f:3fff h 1f:2000 h sa1 - 8k df:1fff h df:0000 h 1f:1fff h 1f:0000 h sa0 - 8k *1 de:ffff h de:0000 h reserved *1: sector sa0 contains the rom con?uration block rcba at cpu address df:0000 h - df:007f h preliminary mb96390 series 22 fme-mb96390 rev 3 serial programming communication interface note: if a flash programmer and its software needs to use a handshaking pin, fujitsu suggests to the tool vendor to support at least port p00_1 on pin 88. if handshaking is used by the tool but p00_1 is not available in customer s application, fujitsu suggests to the customer to check the tool manual or to contact the tool vendor for alternative handshaking pins. usart pins for flash serial programming (md[2:0] = 010, serial communication mode) mb96f39x pin number usart number normal function lqfp-100 8 usart0 sin0 9sot0 10 sck0 3 usart1 sin1 4sot1 5 sck1 46 usart2 sin2 47 sot2 48 sck2 preliminary mb96390 series fme-mb96390 rev 3 23 i/o map i/o map mb96f39x (1 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access 000000 h i/o port p00 - port data register pdr00 r/w 000001 h i/o port p01 - port data register pdr01 r/w 000002 h i/o port p02 - port data register pdr02 r/w 000003 h i/o port p03 - port data register pdr03 r/w 000004 h i/o port p04 - port data register pdr04 r/w 000005 h i/o port p05 - port data register pdr05 r/w 000006 h i/o port p06 - port data register pdr06 r/w 000007 h reserved - 000008 h i/o port p08 - port data register pdr08 r/w 000009 h i/o port p09 - port data register pdr09 r/w 00000a h i/o port p10 - port data register pdr10 r/w 00000b h i/o port p11 - port data register pdr11 r/w 00000c h i/o port p12 - port data register pdr12 r/w 00000d h i/o port p13 - port data register pdr13 r/w 00000e h - 000017 h reserved - 000018 h adc0 - control status register low adcsl adcs r/w 000019 h adc0 - control status register high adcsh r/w 00001a h adc0 - data register low adcrl adcr r 00001b h adc0 - data register high adcrh r 00001c h adc0 - setting register adsr r/w 00001d h adc0 - setting register r/w 00001e h adc0 - extended con?uration register adecr r/w 00001f h reserved - 000020 h frt0 - data register of free-running timer tcdt0 r/w 000021 h frt0 - data register of free-running timer r/w 000022 h frt0 - control status register of free-running timer low tccsl0 tccs0 r/w 000023 h frt0 - control status register of free-running timer high tccsh0 r/w preliminary mb96390 series 24 fme-mb96390 rev 3 000024 h frt1 - data register of free-running timer tcdt1 r/w 000025 h frt1 - data register of free-running timer r/w 000026 h frt1 - control status register of free-running timer low tccsl1 tccs1 r/w 000027 h frt1 - control status register of free-running timer high tccsh1 r/w 000028 h ocu0 - output compare control status ocs0 r/w 000029 h ocu1 - output compare control status ocs1 r/w 00002a h ocu0 - compare register occp0 r/w 00002b h ocu0 - compare register r/w 00002c h ocu1 - compare register occp1 r/w 00002d h ocu1 - compare register r/w 00002e h ocu2 - output compare control status ocs2 r/w 00002f h ocu3 - output compare control status ocs3 r/w 000030 h ocu2 - compare register occp2 r/w 000031 h ocu2 - compare register r/w 000032 h ocu3 - compare register occp3 r/w 000033 h ocu3 - compare register r/w 000034 h - 00003f h reserved - 000040 h icu0/icu1 - control status register ics01 r/w 000041 h icu0/icu1 - edge register ice01 r/w 000042 h icu0 - capture register low ipcpl0 ipcp0 r 000043 h icu0 - capture register high ipcph0 r 000044 h icu1 - capture register low ipcpl1 ipcp1 r 000045 h icu1 - capture register high ipcph1 r 000046 h - 000051 h reserved - 000052 h icu6/icu7 - control status register ics67 r/w 000053 h icu6/icu7 - edge register ice67 r/w 000054 h icu6 - capture register low ipcpl6 ipcp6 r i/o map mb96f39x (2 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series fme-mb96390 rev 3 25 000055 h icu6 - capture register high ipcph6 r 000056 h icu7 - capture register low ipcpl7 ipcp7 r 000057 h icu7 - capture register high ipcph7 r 000058 h extint0 - external interrupt enable register enir0 r/w 000059 h extint0 - external interrupt interrupt request register eirr0 r/w 00005a h extint0 - external interrupt level select low elvrl0 elvr0 r/w 00005b h extint0 - external interrupt level select high elvrh0 r/w 00005c h - 00005f h reserved - 000060 h rlt0 - timer control status register low tmcsrl0 tmcsr0 r/w 000061 h rlt0 - timer control status register high tmcsrh0 r/w 000062 h rlt0 - reload register - for writing tmrlr0 w 000062 h rlt0 - reload register - for reading tmr0 r 000063 h rlt0 - reload register - for writing w 000063 h rlt0 - reload register - for reading r 000064 h rlt1 - timer control status register low tmcsrl1 tmcsr1 r/w 000065 h rlt1 - timer control status register high tmcsrh1 r/w 000066 h rlt1 - reload register - for writing tmrlr1 w 000066 h rlt1 - reload register - for reading tmr1 r 000067 h rlt1 - reload register - for writing w 000067 h rlt1 - reload register - for reading r 000068 h rlt2 - timer control status register low tmcsrl2 tmcsr2 r/w 000069 h rlt2 - timer control status register high tmcsrh2 r/w 00006a h rlt2 - reload register - for writing tmrlr2 w 00006a h rlt2 - reload register - for reading tmr2 r 00006b h rlt2 - reload register - for writing w 00006b h rlt2 - reload register - for reading r 00006c h rlt3 - timer control status register low tmcsrl3 tmcsr3 r/w 00006d h rlt3 - timer control status register high tmcsrh3 r/w 00006e h rlt3 - reload register - for writing tmrlr3 w i/o map mb96f39x (3 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series 26 fme-mb96390 rev 3 00006e h rlt3 - reload register - for reading tmr3 r 00006f h rlt3 - reload register - for writing w 00006f h rlt3 - reload register - for reading r 000070 h rlt6 - timer control status register low (dedic. rlt for ppg) tmcsrl6 tmcsr6 r/w 000071 h rlt6 - timer control status register high (dedic. rlt for ppg) tmcsrh6 r/w 000072 h rlt6 - reload register (dedic. rlt for ppg) - for writing tmrlr6 w 000072 h rlt6 - reload register (dedic. rlt for ppg) - for reading tmr6 r 000073 h rlt6 - reload register (dedic. rlt for ppg) - for writing w 000073 h rlt6 - reload register (dedic. rlt for ppg) - for reading r 000074 h ppg3-ppg0 - general control register 1 low gcn1l0 gcn10 r/w 000075 h ppg3-ppg0 - general control register 1 high gcn1h0 r/w 000076 h ppg3-ppg0 - general control register 2 low gcn2l0 gcn20 r/w 000077 h ppg3-ppg0 - general control register 2 high gcn2h0 r/w 000078 h ppg0 - timer register ptmr0 r 000079 h ppg0 - timer register r 00007a h ppg0 - period setting register pcsr0 w 00007b h ppg0 - period setting register w 00007c h ppg0 - duty cycle register pdut0 w 00007d h ppg0 - duty cycle register w 00007e h ppg0 - control status register low pcnl0 pcn0 r/w 00007f h ppg0 - control status register high pcnh0 r/w 000080 h ppg1 - timer register ptmr1 r 000081 h ppg1 - timer register r 000082 h ppg1 - period setting register pcsr1 w 000083 h ppg1 - period setting register w 000084 h ppg1 - duty cycle register pdut1 w i/o map mb96f39x (4 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series fme-mb96390 rev 3 27 000085 h ppg1 - duty cycle register w 000086 h ppg1 - control status register low pcnl1 pcn1 r/w 000087 h ppg1 - control status register high pcnh1 r/w 000088 h ppg2 - timer register ptmr2 r 000089 h ppg2 - timer register r 00008a h ppg2 - period setting register pcsr2 w 00008b h ppg2 - period setting register w 00008c h ppg2 - duty cycle register pdut2 w 00008d h ppg2 - duty cycle register w 00008e h ppg2 - control status register low pcnl2 pcn2 r/w 00008f h ppg2 - control status register high pcnh2 r/w 000090 h ppg3 - timer register ptmr3 r 000091 h ppg3 - timer register r 000092 h ppg3 - period setting register pcsr3 w 000093 h ppg3 - period setting register w 000094 h ppg3 - duty cycle register pdut3 w 000095 h ppg3 - duty cycle register w 000096 h ppg3 - control status register low pcnl3 pcn3 r/w 000097 h ppg3 - control status register high pcnh3 r/w 000098 h - 0000ab h reserved - 0000ac h i2c0 - bus status register ibsr0 r 0000ad h i2c0 - bus control register ibcr0 r/w 0000ae h i2c0 - ten bit slave address register low itbal0 itba0 r/w 0000af h i2c0 - ten bit slave address register high itbah0 r/w 0000b0 h i2c0 - ten bit address mask register low itmkl0 itmk0 r/w 0000b1 h i2c0 - ten bit address mask register high itmkh0 r/w 0000b2 h i2c0 - seven bit slave address register isba0 r/w 0000b3 h i2c0 - seven bit address mask register ismk0 r/w 0000b4 h i2c0 - data register idar0 r/w i/o map mb96f39x (5 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series 28 fme-mb96390 rev 3 0000b5 h i2c0 - clock control register iccr0 r/w 0000b6 h - 0000bf h reserved - 0000c0 h usart0 - serial mode register smr0 r/w 0000c1 h usart0 - serial control register scr0 r/w 0000c2 h usart0 - tx register tdr0 w 0000c2 h usart0 - rx register rdr0 r 0000c3 h usart0 - serial status ssr0 r/w 0000c4 h usart0 - control/com. register eccr0 r/w 0000c5 h usart0 - ext. status register escr0 r/w 0000c6 h usart0 - baud rate generator register low bgrl0 bgr0 r/w 0000c7 h usart0 - baud rate generator register high bgrh0 r/w 0000c8 h usart0 - extended serial interrupt register esir0 r/w 0000c9 h reserved - 0000ca h usart1 - serial mode register smr1 r/w 0000cb h usart1 - serial control register scr1 r/w 0000cc h usart1 - tx register tdr1 w 0000cc h usart1 - rx register rdr1 r 0000cd h usart1 - serial status ssr1 r/w 0000ce h usart1 - control/com. register eccr1 r/w 0000cf h usart1 - ext. status register escr1 r/w 0000d0 h usart1 - baud rate generator register low bgrl1 bgr1 r/w 0000d1 h usart1 - baud rate generator register high bgrh1 r/w 0000d2 h usart1 - extended serial interrupt register esir1 r/w 0000d3 h reserved - 0000d4 h usart2 - serial mode register smr2 r/w 0000d5 h usart2 - serial control register scr2 r/w 0000d6 h usart2 - tx register tdr2 w 0000d6 h usart2 - rx register rdr2 r 0000d7 h usart2 - serial status ssr2 r/w i/o map mb96f39x (6 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series fme-mb96390 rev 3 29 0000d8 h usart2 - control/com. register eccr2 r/w 0000d9 h usart2 - ext. status register escr2 r/w 0000da h usart2 - baud rate generator register low bgrl2 bgr2 r/w 0000db h usart2 - baud rate generator register high bgrh2 r/w 0000dc h usart2 - extended serial interrupt register esir2 r/w 0000dd h - 00017f h reserved - 000180 h - 00037f h cpu - general purpose registers (ram access) gpr_ram r/w 000380 h - 00039f h reserved - 0003a0 h interrupt level register ilr icr r/w 0003a1 h interrupt index register idx r/w 0003a2 h interrupt vector table base register low tbrl tbr r/w 0003a3 h interrupt vector table base register high tbrh r/w 0003a4 h delayed interrupt register dirr r/w 0003a5 h non maskable interrupt register nmi r/w 0003a6 h - 0003ab h reserved - 0003ac h edsu communication interrupt selection low edsu2l edsu2 r/w 0003ad h edsu communication interrupt selection high edsu2h r/w 0003ae h rom mirror control register romm r/w 0003af h edsu con?uration register edsu r/w 0003b0 h memory patch control/status register ch 0/1 pfcs0 r/w 0003b1 h memory patch control/status register ch 0/1 r/w 0003b2 h memory patch control/status register ch 2/3 pfcs1 r/w 0003b3 h memory patch control/status register ch 2/3 r/w 0003b4 h memory patch control/status register ch 4/5 pfcs2 r/w 0003b5 h memory patch control/status register ch 4/5 r/w 0003b6 h memory patch control/status register ch 6/7 pfcs3 r/w 0003b7 h memory patch control/status register ch 6/7 r/w i/o map mb96f39x (7 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series 30 fme-mb96390 rev 3 0003b8 h memory patch function - patch address 0 low pfal0 r/w 0003b9 h memory patch function - patch address 0 middle pfam0 r/w 0003ba h memory patch function - patch address 0 high pfah0 r/w 0003bb h memory patch function - patch address 1 low pfal1 r/w 0003bc h memory patch function - patch address 1 middle pfam1 r/w 0003bd h memory patch function - patch address 1 high pfah1 r/w 0003be h memory patch function - patch address 2 low pfal2 r/w 0003bf h memory patch function - patch address 2 middle pfam2 r/w 0003c0 h memory patch function - patch address 2 high pfah2 r/w 0003c1 h memory patch function - patch address 3 low pfal3 r/w 0003c2 h memory patch function - patch address 3 middle pfam3 r/w 0003c3 h memory patch function - patch address 3 high pfah3 r/w 0003c4 h memory patch function - patch address 4 low pfal4 r/w 0003c5 h memory patch function - patch address 4 middle pfam4 r/w 0003c6 h memory patch function - patch address 4 high pfah4 r/w 0003c7 h memory patch function - patch address 5 low pfal5 r/w 0003c8 h memory patch function - patch address 5 middle pfam5 r/w 0003c9 h memory patch function - patch address 5 high pfah5 r/w 0003ca h memory patch function - patch address 6 low pfal6 r/w 0003cb h memory patch function - patch address 6 middle pfam6 r/w 0003cc h memory patch function - patch address 6 high pfah6 r/w 0003cd h memory patch function - patch address 7 low pfal7 r/w 0003ce h memory patch function - patch address 7 middle pfam7 r/w 0003cf h memory patch function - patch address 7 high pfah7 r/w 0003d0 h memory patch function - patch data 0 low pfdl0 pfd0 r/w 0003d1 h memory patch function - patch data 0 high pfdh0 r/w 0003d2 h memory patch function - patch data 1 low pfdl1 pfd1 r/w 0003d3 h memory patch function - patch data 1 high pfdh1 r/w 0003d4 h memory patch function - patch data 2 low pfdl2 pfd2 r/w 0003d5 h memory patch function - patch data 2 high pfdh2 r/w i/o map mb96f39x (8 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series fme-mb96390 rev 3 31 0003d6 h memory patch function - patch data 3 low pfdl3 pfd3 r/w 0003d7 h memory patch function - patch data 3 high pfdh3 r/w 0003d8 h memory patch function - patch data 4 low pfdl4 pfd4 r/w 0003d9 h memory patch function - patch data 4 high pfdh4 r/w 0003da h memory patch function - patch data 5 low pfdl5 pfd5 r/w 0003db h memory patch function - patch data 5 high pfdh5 r/w 0003dc h memory patch function - patch data 6 low pfdl6 pfd6 r/w 0003dd h memory patch function - patch data 6 high pfdh6 r/w 0003de h memory patch function - patch data 7 low pfdl7 pfd7 r/w 0003df h memory patch function - patch data 7 high pfdh7 r/w 0003e0 h - 0003f0 h reserved - 0003f1 h memory control status register a mcsra r/w 0003f2 h memory timing con?uration register a low mtcral mtcra r/w 0003f3 h memory timing con?uration register a high mtcrah r/w 0003f4 h - 0003f7 h reserved - 0003f8 h flash memory write control register 0 fmwc0 r/w 0003f9 h flash memory write control register 1 fmwc1 r/w 0003fa h flash memory write control register 2 fmwc2 r/w 0003fb h flash memory write control register 3 fmwc3 r/w 0003fc h flash memory write control register 4 fmwc4 r/w 0003fd h flash memory write control register 5 fmwc5 r/w 0003fe h - 0003ff h reserved - 000400 h standby mode control register smcr r/w 000401 h clock select register cksr r/w 000402 h clock stabilization select register ckssr r/w 000403 h clock monitor register ckmr r 000404 h clock frequency control register low ckfcrl ckfcr r/w 000405 h clock frequency control register high ckfcrh r/w i/o map mb96f39x (9 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series 32 fme-mb96390 rev 3 000406 h pll control register low pllcrl pllcr r/w 000407 h pll control register high pllcrh r/w 000408 h rc clock timer control register rctcr r/w 000409 h main clock timer control register mctcr r/w 00040a h sub clock timer control register sctcr r/w 00040b h reset cause and clock status register with clear function rccsrc r 00040c h reset con?uration register rcr r/w 00040d h reset cause and clock status register rccsr r 00040e h watch dog timer con?uration register wdtc r/w 00040f h watch dog timer clear pattern register wdtcp w 000410 h - 000414 h reserved - 000415 h clock output activation register coar r/w 000416 h clock output con?uration register 0 cocr0 r/w 000417 h clock output con?uration register 1 cocr1 r/w 000418 h clock modulator control register cmcr r/w 000419 h reserved - 00041a h clock modulator parameter register low cmprl cmpr r/w 00041b h clock modulator parameter register high cmprh r/w 00041c h - 00042b h reserved - 00042c h voltage regulator control register vrcr r/w 00042d h clock input and lvd control register cilcr r/w 00042e h - 00042f h reserved - 000430 h i/o port p00 - data direction register ddr00 r/w 000431 h i/o port p01 - data direction register ddr01 r/w 000432 h i/o port p02 - data direction register ddr02 r/w 000433 h i/o port p03 - data direction register ddr03 r/w 000434 h i/o port p04 - data direction register ddr04 r/w i/o map mb96f39x (10 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series fme-mb96390 rev 3 33 000435 h i/o port p05 - data direction register ddr05 r/w 000436 h i/o port p06 - data direction register ddr06 r/w 000437 h reserved - 000438 h i/o port p08 - data direction register ddr08 r/w 000439 h i/o port p09 - data direction register ddr09 r/w 00043a h i/o port p10 - data direction register ddr10 r/w 00043b h i/o port p11 - data direction register ddr11 r/w 00043c h i/o port p12 - data direction register ddr12 r/w 00043d h i/o port p13 - data direction register ddr13 r/w 00043e h - 000443 h reserved - 000444 h i/o port p00 - port input enable register pier00 r/w 000445 h i/o port p01 - port input enable register pier01 r/w 000446 h i/o port p02 - port input enable register pier02 r/w 000447 h i/o port p03 - port input enable register pier03 r/w 000448 h i/o port p04 - port input enable register pier04 r/w 000449 h i/o port p05 - port input enable register pier05 r/w 00044a h i/o port p06 - port input enable register pier06 r/w 00044b h reserved - 00044c h i/o port p08 - port input enable register pier08 r/w 00044d h i/o port p09 - port input enable register pier09 r/w 00044e h i/o port p10 - port input enable register pier10 r/w 00044f h i/o port p11 - port input enable register pier11 r/w 000450 h i/o port p12 - port input enable register pier12 r/w 000451 h i/o port p13 - port input enable register pier13 r/w 000452 h - 000457 h reserved - 000458 h i/o port p00 - port input level register pilr00 r/w 000459 h i/o port p01 - port input level register pilr01 r/w 00045a h i/o port p02 - port input level register pilr02 r/w 00045b h i/o port p03 - port input level register pilr03 r/w i/o map mb96f39x (11 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series 34 fme-mb96390 rev 3 00045c h i/o port p04 - port input level register pilr04 r/w 00045d h i/o port p05 - port input level register pilr05 r/w 00045e h i/o port p06 - port input level register pilr06 r/w 00045f h reserved - 000460 h i/o port p08 - port input level register pilr08 r/w 000461 h i/o port p09 - port input level register pilr09 r/w 000462 h i/o port p10 - port input level register pilr10 r/w 000463 h i/o port p11 - port input level register pilr11 r/w 000464 h i/o port p12 - port input level register pilr12 r/w 000465 h i/o port p13 - port input level register pilr13 r/w 000466 h - 00046b h reserved - 00046c h i/o port p00 - extended port input level register epilr00 r/w 00046d h i/o port p01 - extended port input level register epilr01 r/w 00046e h i/o port p02 - extended port input level register epilr02 r/w 00046f h i/o port p03 - extended port input level register epilr03 r/w 000470 h i/o port p04 - extended port input level register epilr04 r/w 000471 h i/o port p05 - extended port input level register epilr05 r/w 000472 h i/o port p06 - extended port input level register epilr06 r/w 000473 h reserved - 000474 h i/o port p08 - extended port input level register epilr08 r/w 000475 h i/o port p09 - extended port input level register epilr09 r/w 000476 h i/o port p10 - extended port input level register epilr10 r/w 000477 h i/o port p11 - extended port input level register epilr11 r/w 000478 h i/o port p12 - extended port input level register epilr12 r/w 000479 h i/o port p13 - extended port input level register epilr13 r/w 00047a h - 00047f h reserved - 000480 h i/o port p00 - port output drive register podr00 r/w 000481 h i/o port p01 - port output drive register podr01 r/w 000482 h i/o port p02 - port output drive register podr02 r/w i/o map mb96f39x (12 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series fme-mb96390 rev 3 35 000483 h i/o port p03 - port output drive register podr03 r/w 000484 h i/o port p04 - port output drive register podr04 r/w 000485 h i/o port p05 - port output drive register podr05 r/w 000486 h i/o port p06 - port output drive register podr06 r/w 000487 h reserved - 000488 h i/o port p08 - port output drive register podr08 r/w 000489 h i/o port p09 - port output drive register podr09 r/w 00048a h i/o port p10 - port output drive register podr10 r/w 00048b h i/o port p11 - port output drive register podr11 r/w 00048c h i/o port p12 - port output drive register podr12 r/w 00048d h i/o port p13 - port output drive register podr13 r/w 00048e h - 00049b h reserved - 00049c h i/o port p08 - port high drive register phdr08 r/w 00049d h i/o port p09 - port high drive register phdr09 r/w 00049e h i/o port p10 - port high drive register phdr10 r/w 00049f h - 0004a7 h reserved - 0004a8 h i/o port p00 - pull-up resistor control register pucr00 r/w 0004a9 h i/o port p01 - pull-up resistor control register pucr01 r/w 0004aa h i/o port p02 - pull-up resistor control register pucr02 r/w 0004ab h i/o port p03 - pull-up resistor control register pucr03 r/w 0004ac h i/o port p04 - pull-up resistor control register pucr04 r/w 0004ad h i/o port p05 - pull-up resistor control register pucr05 r/w 0004ae h i/o port p06 - pull-up resistor control register pucr06 r/w 0004af h reserved - 0004b0 h i/o port p08 - pull-up resistor control register pucr08 r/w 0004b1 h i/o port p09 - pull-up resistor control register pucr09 r/w 0004b2 h i/o port p10 - pull-up resistor control register pucr10 r/w 0004b3 h i/o port p11 - pull-up resistor control register pucr11 r/w 0004b4 h i/o port p12 - pull-up resistor control register pucr12 r/w i/o map mb96f39x (13 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series 36 fme-mb96390 rev 3 0004b5 h i/o port p13 - pull-up resistor control register pucr13 r/w 0004b6 h - 0004bb h reserved - 0004bc h i/o port p00 - external pin state register epsr00 r 0004bd h i/o port p01 - external pin state register epsr01 r 0004be h i/o port p02 - external pin state register epsr02 r 0004bf h i/o port p03 - external pin state register epsr03 r 0004c0 h i/o port p04 - external pin state register epsr04 r 0004c1 h i/o port p05 - external pin state register epsr05 r 0004c2 h i/o port p06 - external pin state register epsr06 r 0004c3 h reserved - 0004c4 h i/o port p08 - external pin state register epsr08 r 0004c5 h i/o port p09 - external pin state register epsr09 r 0004c6 h i/o port p10 - external pin state register epsr10 r 0004c7 h i/o port p11 - external pin state register epsr11 r 0004c8 h i/o port p12 - external pin state register epsr12 r 0004c9 h i/o port p13 - external pin state register epsr13 r 0004ca h - 0004cf h reserved - 0004d0 h adc analog input enable register 0 ader0 r/w 0004d1 h adc analog input enable register 1 ader1 r/w 0004d2 h adc analog input enable register 2 ader2 r/w 0004d3 h adc analog input enable register 3 ader3 r/w 0004d4 h adc analog input enable register 4 ader4 r/w 0004d5 h reserved - 0004d6 h peripheral resource relocation register 0 prrr0 r/w 0004d7 h peripheral resource relocation register 1 prrr1 r/w 0004d8 h peripheral resource relocation register 2 prrr2 r/w 0004d9 h peripheral resource relocation register 3 prrr3 r/w 0004da h peripheral resource relocation register 4 prrr4 r/w 0004db h peripheral resource relocation register 5 prrr5 r/w i/o map mb96f39x (14 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series fme-mb96390 rev 3 37 0004dc h peripheral resource relocation register 6 prrr6 r/w 0004dd h peripheral resource relocation register 7 prrr7 r/w 0004de h peripheral resource relocation register 8 prrr8 r/w 0004df h peripheral resource relocation register 9 prrr9 r/w 0004e0 h rtc - sub second register l wtbrl0 wtbr0 r/w 0004e1 h rtc - sub second register m wtbrh0 r/w 0004e2 h rtc - sub-second register h wtbr1 r/w 0004e3 h rtc - second register wtsr r/w 0004e4 h rtc - minutes wtmr r/w 0004e5 h rtc - hour wthr r/w 0004e6 h rtc - timer control extended register wtcer r/w 0004e7 h rtc - clock select register wtcksr r/w 0004e8 h rtc - timer control register low wtcrl wtcr r/w 0004e9 h rtc - timer control register high wtcrh r/w 0004ea h cal - calibration unit control register cucr r/w 0004eb h reserved - 0004ec h cal - duration timer data register low cutdl cutd r/w 0004ed h cal - duration timer data register high cutdh r/w 0004ee h cal - calibration timer register 2 low cutr2l cutr2 r 0004ef h cal - calibration timer register 2 high cutr2h r 0004f0 h cal - calibration timer register 1 low cutr1l cutr1 r 0004f1 h cal - calibration timer register 1 high cutr1h r 0004f2 h - 0004f9 h reserved - 0004fa h rlt - timer input select (for cascading) tmisr r/w 0004fb h - 00055f h reserved - 000560 h alarm0 - control status register acsr0 r/w 000561 h alarm0 - extended control status register aecsr0 r/w 000562 h - 0005df h reserved - i/o map mb96f39x (15 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series 38 fme-mb96390 rev 3 0005e0 h smc0 - pwm control register pwc0 r/w 0005e1 h smc0 - extended control register (output enable) pwec0 r/w 0005e2 h smc0 - pwm compare register pwm 1 pwc10 r/w 0005e3 h smc0 - pwm compare register pwm 1 r/w 0005e4 h smc0 - pwm compare register pwm 2 pwc20 r/w 0005e5 h smc0 - pwm compare register pwm 2 r/w 0005e6 h smc0 - pwm select register pws10 r/w 0005e7 h smc0 - pwm select register pws20 r/w 0005e8 h - 0005e9 h reserved - 0005ea h smc1 - pwm control register pwc1 r/w 0005eb h smc1 - extended control register (output enable) pwec1 r/w 0005ec h smc1 - pwm compare register pwm 1 pwc11 r/w 0005ed h smc1 - pwm compare register pwm 1 r/w 0005ee h smc1 - pwm compare register pwm 2 pwc21 r/w 0005ef h smc1 - pwm compare register pwm 2 r/w 0005f0 h smc1 - pwm select register pws11 r/w 0005f1 h smc1 - pwm select register pws21 r/w 0005f2 h - 0005f3 h reserved - 0005f4 h smc2 - pwm control register pwc2 r/w 0005f5 h smc2 - extended control register (output enable) pwec2 r/w 0005f6 h smc2 - pwm compare register pwm 1 pwc12 r/w 0005f7 h smc2 - pwm compare register pwm 1 r/w 0005f8 h smc2 - pwm compare register pwm 2 pwc22 r/w 0005f9 h smc2 - pwm compare register pwm 2 r/w 0005fa h smc2 - pwm select register pws12 r/w 0005fb h smc2 - pwm select register pws22 r/w 0005fc h - 000607 h reserved - 000608 h smc4 - pwm control register pwc4 r/w i/o map mb96f39x (16 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series fme-mb96390 rev 3 39 000609 h smc4 - extended control register (output enable) pwec4 r/w 00060a h smc4 - pwm compare register pwm 1 pwc14 r/w 00060b h smc4 - pwm compare register pwm 1 r/w 00060c h smc4 - pwm compare register pwm 2 pwc24 r/w 00060d h smc4 - pwm compare register pwm 2 r/w 00060e h smc4 - pwm select register pws14 r/w 00060f h smc4 - pwm select register pws24 r/w 000610 h - 00061b h reserved - 00061c h lcd - output enable register 0 (seg 7-0) lcder0 r/w 00061d h lcd - output enable register 1 (seg 15-8) lcder1 r/w 00061e h lcd - output enable register 2 (seg 23-16) lcder2 r/w 00061f h lcd - output enable register 3 (seg 31-24) lcder3 r/w 000620 h lcd - output enable register 4 (seg 39-32) lcder4 r/w 000621 h lcd - output enable register 5 (seg 47-40) lcder5 r/w 000622 h lcd - output enable register 6 (seg 55-48) lcder6 r/w 000623 h lcd - output enable register 7 (seg 63-56) lcder7 r/w 000624 h lcd - output enable register 8 (seg 71-64) lcder8 r/w 000625 h reserved - 000626 h lcd - output enable register v (vx) lcdver r/w 000627 h lcd - extended control register lecr r/w 000628 h lcd - common pin switching register lcdcmr r/w 000629 h lcd - control register lcr r/w 00062a h lcd - data register for segment 1-0 vram0 r/w 00062b h lcd - data register for segment 3-2 vram1 r/w 00062c h lcd - data register for segment 5-4 vram2 r/w 00062d h lcd - data register for segment 7-6 vram3 r/w 00062e h lcd - data register for segment 9-8 vram4 r/w 00062f h lcd - data register for segment 11-10 vram5 r/w 000630 h lcd - data register for segment 13-12 vram6 r/w i/o map mb96f39x (17 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series 40 fme-mb96390 rev 3 000631 h lcd - data register for segment 15-14 vram7 r/w 000632 h lcd - data register for segment 17-16 vram8 r/w 000633 h lcd - data register for segment 19-18 vram9 r/w 000634 h lcd - data register for segment 21-20 vram10 r/w 000635 h lcd - data register for segment 23-22 vram11 r/w 000636 h lcd - data register for segment 25-24 vram12 r/w 000637 h lcd - data register for segment 27-26 vram13 r/w 000638 h lcd - data register for segment 29-28 vram14 r/w 000639 h lcd - data register for segment 31-30 vram15 r/w 00063a h lcd - data register for segment 33-32 vram16 r/w 00063b h lcd - data register for segment 35-34 vram17 r/w 00063c h lcd - data register for segment 37-36 vram18 r/w 00063d h lcd - data register for segment 39-38 vram19 r/w 00063e h lcd - data register for segment 41-40 vram20 r/w 00063f h lcd - data register for segment 43-42 vram21 r/w 000640 h lcd - data register for segment 45-44 vram22 r/w 000641 h lcd - data register for segment 47-46 vram23 r/w 000642 h lcd - data register for segment 49-48 vram24 r/w 000643 h lcd - data register for segment 51-50 vram25 r/w 000644 h lcd - data register for segment 53-52 vram26 r/w 000645 h lcd - data register for segment 55-54 vram27 r/w 000646 h lcd - data register for segment 57-56 vram28 r/w 000647 h lcd - data register for segment 59-58 vram29 r/w 000648 h lcd - data register for segment 61-60 vram30 r/w 000649 h lcd - data register for segment 63-62 vram31 r/w 00064a h lcd - data register for segment 65-64 vram32 r/w 00064b h - 00065f h reserved - 000660 h peripheral resource relocation register 10 prrr10 r/w 000661 h peripheral resource relocation register 11 prrr11 r/w i/o map mb96f39x (18 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series fme-mb96390 rev 3 41 000662 h peripheral resource relocation register 12 prrr12 r/w 000663 h peripheral resource relocation register 13 prrr13 w 000664 h - 0006ff h reserved - 000700 h can0 - control register low ctrlrl0 ctrlr0 r/w 000701 h can0 - control register high (reserved) ctrlrh0 r 000702 h can0 - status register low statrl0 statr0 r/w 000703 h can0 - status register high (reserved) statrh0 r 000704 h can0 - error counter low (transmit) errcntl0 errcnt0 r 000705 h can0 - error counter high (receive) errcnth0 r 000706 h can0 - bit timing register low btrl0 btr0 r/w 000707 h can0 - bit timing register high btrh0 r/w 000708 h can0 - interrupt register low intrl0 intr0 r 000709 h can0 - interrupt register high intrh0 r 00070a h can0 - test register low testrl0 testr0 r/w 00070b h can0 - test register high (reserved) testrh0 r 00070c h can0 - brp extension register low brperl0 brper0 r/w 00070d h can0 - brp extension register high (reserved) brperh0 r 00070e h - 00070f h reserved - 000710 h can0 - if1 command request register low if1creql0 if1creq0 r/w 000711 h can0 - if1 command request register high if1creqh0 r/w 000712 h can0 - if1 command mask register low if1cmskl0 if1cmsk0 r/w 000713 h can0 - if1 command mask register high (re- served) if1cmskh0 r 000714 h can0 - if1 mask 1 register low if1msk1l0 if1msk10 r/w 000715 h can0 - if1 mask 1 register high if1msk1h0 r/w 000716 h can0 - if1 mask 2 register low if1msk2l0 if1msk20 r/w 000717 h can0 - if1 mask 2 register high if1msk2h0 r/w 000718 h can0 - if1 arbitration 1 register low if1arb1l0 if1arb10 r/w 000719 h can0 - if1 arbitration 1 register high if1arb1h0 r/w i/o map mb96f39x (19 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series 42 fme-mb96390 rev 3 00071a h can0 - if1 arbitration 2 register low if1arb2l0 if1arb20 r/w 00071b h can0 - if1 arbitration 2 register high if1arb2h0 r/w 00071c h can0 - if1 message control register low if1mctrl0 if1mctr0 r/w 00071d h can0 - if1 message control register high if1mctrh0 r/w 00071e h can0 - if1 data a1 low if1dta1l0 if1dta10 r/w 00071f h can0 - if1 data a1 high if1dta1h0 r/w 000720 h can0 - if1 data a2 low if1dta2l0 if1dta20 r/w 000721 h can0 - if1 data a2 high if1dta2h0 r/w 000722 h can0 - if1 data b1 low if1dtb1l0 if1dtb10 r/w 000723 h can0 - if1 data b1 high if1dtb1h0 r/w 000724 h can0 - if1 data b2 low if1dtb2l0 if1dtb20 r/w 000725 h can0 - if1 data b2 high if1dtb2h0 r/w 000726 h - 00073f h reserved - 000740 h can0 - if2 command request register low if2creql0 if2creq0 r/w 000741 h can0 - if2 command request register high if2creqh0 r/w 000742 h can0 - if2 command mask register low if2cmskl0 if2cmsk0 r/w 000743 h can0 - if2 command mask register high (re- served) if2cmskh0 r 000744 h can0 - if2 mask 1 register low if2msk1l0 if2msk10 r/w 000745 h can0 - if2 mask 1 register high if2msk1h0 r/w 000746 h can0 - if2 mask 2 register low if2msk2l0 if2msk20 r/w 000747 h can0 - if2 mask 2 register high if2msk2h0 r/w 000748 h can0 - if2 arbitration 1 register low if2arb1l0 if2arb10 r/w 000749 h can0 - if2 arbitration 1 register high if2arb1h0 r/w 00074a h can0 - if2 arbitration 2 register low if2arb2l0 if2arb20 r/w 00074b h can0 - if2 arbitration 2 register high if2arb2h0 r/w 00074c h can0 - if2 message control register low if2mctrl0 if2mctr0 r/w 00074d h can0 - if2 message control register high if2mctrh0 r/w 00074e h can0 - if2 data a1 low if2dta1l0 if2dta10 r/w 00074f h can0 - if2 data a1 high if2dta1h0 r/w i/o map mb96f39x (20 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series fme-mb96390 rev 3 43 000750 h can0 - if2 data a2 low if2dta2l0 if2dta20 r/w 000751 h can0 - if2 data a2 high if2dta2h0 r/w 000752 h can0 - if2 data b1 low if2dtb1l0 if2dtb10 r/w 000753 h can0 - if2 data b1 high if2dtb1h0 r/w 000754 h can0 - if2 data b2 low if2dtb2l0 if2dtb20 r/w 000755 h can0 - if2 data b2 high if2dtb2h0 r/w 000756 h - 00077f h reserved - 000780 h can0 - transmission request 1 register low treqr1l0 treqr10 r 000781 h can0 - transmission request 1 register high treqr1h0 r 000782 h can0 - transmission request 2 register low treqr2l0 treqr20 r 000783 h can0 - transmission request 2 register high treqr2h0 r 000784 h - 00078f h reserved - 000790 h can0 - new data 1 register low newdt1l0 newdt10 r 000791 h can0 - new data 1 register high newdt1h0 r 000792 h can0 - new data 2 register low newdt2l0 newdt20 r 000793 h can0 - new data 2 register high newdt2h0 r 000794 h - 00079f h reserved - 0007a0 h can0 - interrupt pending 1 register low intpnd1l0 intpnd10 r 0007a1 h can0 - interrupt pending 1 register high intpnd1h0 r 0007a2 h can0 - interrupt pending 2 register low intpnd2l0 intpnd20 r 0007a3 h can0 - interrupt pending 2 register high intpnd2h0 r 0007a4 h - 0007af h reserved - 0007b0 h can0 - message valid 1 register low msgval1l0 msgval10 r 0007b1 h can0 - message valid 1 register high msgval1h0 r 0007b2 h can0 - message valid 2 register low msgval2l0 msgval20 r 0007b3 h can0 - message valid 2 register high msgval2h0 r 0007b4 h - 0007cd h reserved - i/o map mb96f39x (21 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series 44 fme-mb96390 rev 3 note: any write access to reserved addresses in the i/o map should not be performed. a read access to a reserved address results in reading ?? registers of resources which are described in this table, but which are not supported by the device, should also be handled as ?eserved? 0007ce h can0 - output enable register coer0 r/w 0007cf h reserved - 0007d0 h sg0 - sound generator control register low sgcrl0 sgcr0 r/w 0007d1 h sg0 - sound generator control register high sgcrh0 r/w 0007d2 h sg0 - sound generator frequency register sgfr0 r/w 0007d3 h sg0 - sound generator amplitude register sgar0 r/w 0007d4 h sg0 - sound generator decrement register sgdr0 r/w 0007d5 h sg0 - sound generator tone register sgtr0 r/w 0007d6 h - 000bff h reserved - i/o map mb96f39x (22 of 22) address register abbreviation 8-bit access abbreviation 16-bit access access preliminary mb96390 series fme-mb96390 rev 3 45 interrupt vector table interrupt vector table mb96(f)39x (1 of 3) vector number offset in vector ta- ble vector name index in icr to pro- gram description 0 3fc h callv0 - 1 3f8 h callv1 - 2 3f4 h callv2 - 3 3f0 h callv3 - 4 3ec h callv4 - 5 3e8 h callv5 - 6 3e4 h callv6 - 7 3e0 h callv7 - 8 3dc h reset - 9 3d8 h int9 - 10 3d4 h exception - 11 3d0 h nmi - non-maskable interrupt 12 3cc h dly 12 delayed interrupt 13 3c8 h rc_timer 13 rc timer 14 3c4 h mc_timer 14 main clock timer 15 3c0 h sc_timer 15 sub clock timer 16 3bc h reserved 17 3b8 h extint0 17 external interrupt 0 18 3b4 h extint1 18 external interrupt 1 19 3b0 h extint2 19 external interrupt 2 20 3ac h extint3 20 external interrupt 3 21 3a8 h extint4 21 external interrupt 4 22 3a4 h extint5 22 external interrupt 5 23 3a0 h extint6 23 external interrupt 6 24 39c h extint7 24 external interrupt 7 25 398 h can0 25 can controller 0 26 394 h reserved 27 390 h ppg0 27 programmable pulse generator 0 28 38c h ppg1 28 programmable pulse generator 1 29 388 h ppg2 29 programmable pulse generator 2 30 384 h ppg3 30 programmable pulse generator 3 31 380 h reserved 32 37c h reserved preliminary mb96390 series 46 fme-mb96390 rev 3 33 378 h reserved 34 374 h reserved 35 370 h rlt0 35 reload timer 0 36 36c h rlt1 36 reload timer 1 37 368 h rlt2 37 reload timer 2 38 364 h rlt3 38 reload timer 3 39 360 h ppgrlt 39 reload timer 6 - dedicated for ppg 40 35c h icu0 40 input capture unit 0 41 358 h icu1 41 input capture unit 1 42 354 h reserved 43 350 h reserved 44 34c h reserved 45 348 h reserved 46 344 h icu6 46 input capture unit 6 47 340 h icu7 47 input capture unit 7 48 33c h ocu0 48 output compare unit 0 49 338 h ocu1 49 output compare unit 1 50 334 h ocu2 50 output compare unit 2 51 330 h ocu3 51 output compare unit 3 52 32c h frt0 52 free running timer 0 53 328 h frt1 53 free running timer 1 54 324 h rtc0 54 real timer clock 55 320 h cal0 55 clock calibration unit 56 31c h sg0 56 sound generator 0 57 318 h reserved 58 314 h iic0 58 i2c interface 59 310 h adc0 59 a/d converter 60 30c h alarm0 60 alarm comparator 0 61 308 h reserved 62 304 h linr0 62 lin usart 0 rx 63 300 h lint0 63 lin usart 0 tx 64 2fc h linr1 64 lin usart 1 rx 65 2f8 h lint1 65 lin usart 1 tx 66 2f4 h linr2 66 lin usart 2 rx 67 2f0 h lint2 67 lin usart 2 tx interrupt vector table mb96(f)39x (2 of 3) vector number offset in vector ta- ble vector name index in icr to pro- gram description preliminary mb96390 series fme-mb96390 rev 3 47 68 2ec h reserved 69 2e8 h reserved 70 2e4 h reserved 71 2e0 h reserved 72 2dc h flash_a 72 flash memory a (only flash devices) 73 2d8 h reserved interrupt vector table mb96(f)39x (3 of 3) vector number offset in vector ta- ble vector name index in icr to pro- gram description preliminary mb96390 series 48 fme-mb96390 rev 3 handling devices special care is required for the following when handling the device: latch-up prevention unused pins handling external clock usage unused sub clock signal notes on pll clock mode operation power supply pins (v cc /v ss ) crystal oscillator circuit turn on sequence of power supply to a/d converter and analog inputs pin handling when not using the a/d converter notes on energization stabilization of power supply voltage smc power supply pins serial communication 1. latch-up prevention cmos ic chips may suffer latch-up under the following conditions: a voltage higher than v cc or lower than v ss is applied to an input or output pin. a voltage higher than the rated voltage is applied between v cc pins and v ss pins. the av cc power supply is applied before the v cc voltage. latch-up may increase the power supply current dramatically, causing thermal damages to the device. for the same reason, extra care is required to not let the analog power-supply voltage (av cc , avrh) exceed the digital power-supply voltage. 2. unused pins handling unused input pins can be left open when the input is disabled (corresponding bit of port input enable register pier = 0). leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. they must therefore be pulled up or pulled down through resistors. to prevent latch-up, those resistors should be more than 2 k ? . unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. 3. external clock usage the permitted frequency range of an external clock depends on the oscillator type and con?uration. see ac characteristics for detailed modes and frequency limits. single and opposite phase external clocks must be connected as follows: 1. single phase external clock when using a single phase external clock, x0 (x0a) pin must be driven and x1 (x1a) pin left open. x0 x1 preliminary mb96390 series fme-mb96390 rev 3 49 2. opposite phase external clock when using an opposite phase external clock, x1 (x1a) must be supplied with a clock signal which has the opposite phase to the x0 (x0a) pins. 4. unused sub clock signal if the pins x0a and x1a are not connected to an oscillator, a pull-down resistor must be connected on the x0a pin and the x1a pin must be left open. 5. notes on pll clock mode operation if the pll clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating pll. performance of this operation, however, cannot be guaranteed. 6. power supply pins (v cc / v ss ) it is required that all v cc -level as well as all v ss -level power supply pins are at the same potential. if there is more than one v cc or v ss level, the device may operate incorrectly or be damaged even within the guaranteed operating range. v cc and v ss must be connected to the device from the power supply with lowest possible impedance. as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 f between v cc and v ss as close as possible to v cc and v ss pins. 7. crystal oscillator and ceramic resonator circuit noise at x0, x1 pins or x0a, x1a pins might cause abnormal operation. it is required to provide bypass capacitors with shortest possible distance to x0, x1 pins and x0a, x1a pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art work surrounding x0, x1 pins and x0a, x1a pins with a ground area for stabilizing the operation. it is highly recommended to evaluate the quartz/mcu or resonator/mcu system at the quartz or resonator manufacturer, especially when using low-q resonators at higher frequencies. 8. turn on sequence of power supply to a/d converter and analog inputs it is required to turn the a/d converter power supply (av cc , avrh, avrl) and analog inputs (ann) on after turning the digital power supply (v cc ) on. it is also required to turn the digital power off after turning the a/d converter supply and analog inputs off. in this case, the voltage must not exceed avrh or av cc (turning the analog and digital power supplies simultaneously on or off is acceptable). 9. pin handling when not using the a/d converter it is required to connect the unused pins of the a/d converter as av cc = v cc , av ss = avrh = avrl = v ss . 10. notes on power-on to prevent malfunction of the internal voltage regulator, supply voltage pro?e while turning the power supply on should be slower than 50 s from 0.2 v to 2.7 v. x0 x1 preliminary mb96390 series 50 fme-mb96390 rev 3 11. stabilization of power supply voltage if the power supply voltage varies acutely even within the operation safety range of the vcc power supply voltage, a malfunction may occur. the vcc power supply voltage must therefore be stabilized. as stabilization guidelines, the power supply voltage must be stabilized in such a way that vcc ripple ?ctuations (peak to peak value) in the commercial frequencies (50 to 60 hz) fall within 10% of the standard vcc power supply voltage and the transient ?ctuation rate becomes 0.1v/ s or less in instantaneous ?ctuation for power supply switching. 12. smc power supply pins all dv ss pins must be set to the same level as the v ss pins. the dv cc power supply level can be set independently of the v cc power supply level. however note that the smc i/o pin state is unde?ed if dv cc is powered on and v cc is below 3v. to avoid this, we recommend to always power v cc before dv cc . 13. serial communication there is a possibility to receive wrong data due to noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider receiving of wrong data when designing the system. for example apply a checksum and retransmit the data if an error occurs. preliminary mb96390 series fme-mb96390 rev 3 51 electrical characteristics 1. absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v v cc = av cc *1 ad converter voltage references avrh, avrl v ss - 0.3 v ss + 6.0 v av cc avrh, av cc avrl, avrh > avrl, avrl av ss smc power supply dv cc v ss - 0.3 v ss + 6.0 v see *7 lcd power supply voltage v0 to v3 v ss - 0.3 v ss + 6.0 v v0 to v3 must not exceed v cc input voltage v i v ss - 0.3 v ss + 6.0 v v i (d)v cc + 0.3v *2 output voltage v o v ss - 0.3 v ss + 6.0 v v o (d)v cc + 0.3v *2 maximum clamp current i clamp -4.0 +4.0 ma applicable to general purpose i/o pins *3 total maximum clamp current |i clamp | - 40 ma applicable to general purpose i/o pins *3 ??level maximum output current i ol1 - 15 ma normal outputs with driving strength set to 5ma i olsmc - 40 ma high current outputs with driv- ing strength set to 30ma ??level average output current i olav1 - 5 ma normal outputs with driving strength set to 5ma i olavsmc - 30 ma high current outputs with driv- ing strength set to 30ma ??level maximum overall output current i ol1 - 100 ma normal outputs i olsmc - 330 ma high current outputs ??level average overall output current i olav1 - 50 ma normal outputs i olavsmc - 250 ma high current outputs ??level maximum output current i oh1 - -15 ma normal outputs with driving strength set to 5ma i ohsmc - -40 ma high current outputs with driv- ing strength set to 30ma ??level average output current i ohav1 - -5 ma normal outputs with driving strength set to 5ma i ohavsmc - -30 ma high current outputs with driv- ing strength set to 30ma ? level maximum overall output current i oh1 - -100 ma normal outputs i ohsmc - -330 ma high current outputs ??level average overall output current i ohav1 - -50 ma normal outputs i ohasmc - -250 ma high current outputs preliminary mb96390 series 52 fme-mb96390 rev 3 *1: av cc and v cc must be set to the same voltage. it is required that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc neither when the power is switched on. *2: v i and v o should not exceed (d)v cc + 0.3 v. v i should also not exceed the speci?d ratings. however if the maximum current to/from a input is limited by some means with external components, the i clamp rating super- sedes the v i rating. input/output voltages of high current ports depend on dv cc. input/output voltages of standard ports depend on v cc. *3: ? applicable to all general purpose i/o pins (pnn_m) except i/o pins with seg or com functionality. ? use within recommended operating conditions. ? use at dc voltage (current) ? the +b signal should always be applied a limiting resistance placed between the +b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the +b input potential may pass through the protective diode and increase the potential at the vcc pin, and this may affect other devices. ? note that if a +b signal is input when the microcontroller power supply is off (not ?ed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? note that if the +b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be suf?ient to operate the power reset (except devices with persistent low voltage reset in internal vector mode). ? no +b signal must be applied to any lcd i/o pin (including unused seg/com pins). permitted power dissipation (mb96f395) *4 p d - 255 *5 mw t a =105 o c - 510 *5 mw t a =85 o c - 830 *5 mw t a =60 o c - 320 *5 mw t a =125 o c, no flash program/ erase *6 - 575 *5 mw t a =105 o c, no flash program/ erase *6 operating ambient temperature t a 0 +70 o c mb96v300b -40 +105 -40 +125 *6 storage temperature t stg -55 +150 o c parameter symbol rating unit remarks min max preliminary mb96390 series fme-mb96390 rev 3 53 ? sample recommended circuits: *4: the maximum permitted power dissipation depends on the ambient temperature, the air ?w velocity and the thermal conductance of the package on the pcb. the actual power dissipation depends on the customer application and can be calculated as follows: p d = p io + p int p io = (v ol * i ol + v oh * i oh ) (io load power dissipation, sum is performed on all io ports) p int = v cc * (i cc + i a ) (internal power dissipation) i cc is the total core current consumption into v cc as described in the ?c characteristics and depends on the selected operation mode and clock frequency and the usage of functions like flash programming or the clock modulator. i a is the analog current consumption into av cc . *5: worst case value for a package mounted on single layer pcb at speci?d t a without air ?w. *6: please contact fujitsu for reliability limitations when using under these conditions. *7: if dv cc is powered before v cc , then smc i/o pins state is unde?ed. to avoid this, we recommend to always power v cc before dv cc . it is not necessary to set v cc and dv cc to the same value. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch v cc r protective diode limiting resistance +b input (0v to 16v) preliminary mb96390 series 54 fme-mb96390 rev 3 2. recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc , dv cc 3.0 - 5.5 v smoothing capacitor at c pin c s 3.5 4.7 15 f use a x7r ceramic capacitor or a capacitor that has similar fre- quency characteristics preliminary mb96390 series fme-mb96390 rev 3 55 3. dc characteristics (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol pin condition value unit remarks min typ max input h voltage v ih port inputs pnn_m cmos hysteresis 0.8/0.2 input se- lected 0.8 v cc - (d)v cc + 0.3 v cmos hysteresis 0.7/0.3 input se- lected 0.7 v cc - (d)v cc + 0.3 v (d)v cc 4.5v 0.74 v cc - (d)v cc + 0.3 v (d)v cc < 4.5v automotive hysteresis input selected 0.8 v cc - (d)v cc + 0.3 v ttl input select- ed 2.0 - (d)v cc + 0.3 v v ihx0f x0 external clock in ?ast clock input mode 0.8 v cc - v cc + 0.3 v v ihx0s x0,x1, x0a,x1a external clock in ?scillation mode 2.5 - v cc + 0.3 v v ihr rstx - 0.8 v cc - v cc + 0.3 v cmos hysteresis in- put v ihm md2-md0 - v cc - 0.3 - v cc + 0.3 v input l voltage v il port inputs pnn_m cmos hysteresis 0.8/0.2 input se- lected v ss - 0.3 - 0.2 (d)v cc v cmos hysteresis 0.7/0.3 input se- lected v ss - 0.3 - 0.3 (d)v cc v automotive hysteresis input selected v ss - 0.3 - 0.5 (d)v cc v (d)v cc 4.5v v ss - 0.3 - 0.46 (d)v cc (d)v cc < 4.5v ttl input select- ed v ss - 0.3 - 0.8 v v ilx0f x0 external clock in ?ast clock input mode v ss - 0.3 - 0.2 v cc v v ilx0s x0,x1, x0a,x1a external clock in ?scillation mode v ss - 0.3 - 0.4 v v ilr rstx - v ss - 0.3 - 0.2 v cc v cmos hysteresis in- put v ilm md2-md0 - v ss - 0.3 - v ss + 0.3 v preliminary mb96390 series 56 fme-mb96390 rev 3 output h voltage v oh2 normal and high current outputs 4.5v (d)v cc 5.5v i oh = -2ma (d)v cc - 0.5 -- v driving strength set to 2ma (podr:od=1, phdr:hd=0) 3.0v (d)v cc < 4.5v i oh = -1.6ma v oh5 normal and high current outputs 4.5v (d)v cc 5.5v i oh = -5ma (d)v cc - 0.5 -- v driving strength set to 5ma (podr:od=0, phdr:hd=0) 3.0v (d)v cc < 4.5v i oh = -3ma v oh30 high cur- rent out- puts 4.5v dv cc 5.5v i oh = -30ma dv cc - 0.5 -- v driving strength set to 30ma (phdr:hd=1) 3.0v dv cc < 4.5v i oh = -20ma v oh3 3ma out- puts 4.5v v cc 5.5v i oh = -3ma v cc - 0.5 -- v i/o circuit type ? 3.0v v cc < 4.5v i oh = -2ma output l voltage v ol2 normal and high current outputs 4.5v (d)v cc 5.5v i ol = +2ma - - 0.4 v driving strength set to 2ma (podr:od=1, phdr:hd=0) 3.0v (d)v cc < 4.5v i ol = +1.6ma v ol5 normal and high current outputs 4.5v (d)v cc 5.5v i ol = +5ma - - 0.4 v driving strength set to 5ma (podr:od=0, phdr:hd=0) 3.0v (d)v cc < 4.5v i ol = +3ma v ol30 high cur- rent out- puts 4.5v dv cc 5.5v i ol = +30ma - - 0.5 v driving strength set to 30ma (phdr:hd=1) 3.0v dv cc < 4.5v i ol = +20ma v ol3 3ma out- puts 3.0v v cc 5.5v i ol = +3ma - - 0.4 v i/o circuit type ? input leak current i il pnn_m v ss < v i < v cc av ss ,avrl preliminary mb96390 series 58 fme-mb96390 rev 3 (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol condition (at t a ) value remarks typ max unit power supply cur- rent in run modes* i ccpll pll run mode with clks1/2 = clkb = clkp1 = 16mhz, clkp2 = 8mhz 1 flash/rom wait state (clkrc and clksc stopped) +25?c 15 20 ma +125?c 16 22.5 pll run mode with clks1/2 = clkb = clkp1 = 32mhz, clkp2 = 16mhz 2 flash/rom wait states (clkrc and clksc stopped) +25?c 23 29 ma +125?c 24.5 31.5 pll run mode with clks1/2 = 48mhz, clkb = clkp1/2 = 24mhz 0 flash/rom wait states (clkrc and clksc stopped) +25?c 27 39 ma +125?c 28.5 41.5 pll run mode with clks1/2 = 80mhz, clkb = clkp1 = 40mhz, clkp2 = 20mhz 1 flash wait state (clkrc and clksc stopped. core voltage at 1.9v) +25?c 38 51 ma +125?c 39.5 53.5 i ccmain main run mode with clks1/2 = clkb = clkp1/2 = 4mhz 1 flash/rom wait state (clkpll, clksc and clkrc stopped) +25?c 4.2 5.2 ma +125?c 4.7 7 i ccrch rc run mode with clks1/2 = clkb = clkp1/2 = 2mhz 1 flash/rom wait state (clkmc, clkpll and clksc stopped) +25?c 2.7 3.7 ma +125?c 3.2 5.4 preliminary mb96390 series fme-mb96390 rev 3 59 power supply cur- rent in run modes* i ccrcl rc run mode with clks1/2 = clkb = clkp1/2 = 100khz, smcr:lpms = 0 1 flash/rom wait state (clkmc, clkpll and clksc stopped. voltage regulator in high power mode) +25?c 0.4 0.6 ma +125?c 0.9 2.1 rc run mode with clks1/2 = clkb = clkp1/2 = 100khz, smcr:lpms = 1 1 flash/rom wait state (clkmc, clkpll and clksc stopped. voltage regulator in low power mode, no flash program- ming/erasing allowed) +25?c 0.15 0.25 ma +125?c 0.55 1.75 i ccsub sub run mode with clks1/2 = clkb = clkp1/2 = 32khz 1 flash/rom wait state (clkmc, clkpll and clkrc stopped, no flash programming/erasing al- lowed) +25?c 0.1 0.2 ma +125?c 0.5 1.7 (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol condition (at t a ) value remarks typ max unit preliminary mb96390 series 60 fme-mb96390 rev 3 power supply cur- rent in sleep modes* i ccspll pll sleep mode with clks1/2 = clkp1 = 16mhz, clkp2 = 8mhz (clkrc and clksc stopped) +25?c 4 6 ma +125?c 4.6 8 pll sleep mode with clks1/2 = clkp1 = 32mhz, clkp2 = 16mhz (clkrc and clksc stopped) +25?c 7 9.5 ma +125?c 7.6 11.5 pll sleep mode with clks1/2 = 48mhz, clkp1/2 = 24mhz (clkrc and clksc stopped) +25?c 7 9 ma +125?c 7.6 11 pll sleep mode with clks1/2 = 80mhz, clkp1 = 40mhz, clkp2 = 20mhz (clkrc and clksc stopped. core voltage at 1.9v) +25?c 11 13 ma +125?c 11.6 15 i ccsmain main sleep mode with clks1/2 = clkp1/2 = 4mhz (clkpll, clksc and clkrc stopped) +25?c 1.3 1.8 ma +125?c 1.8 3.3 i ccsrch rc sleep mode with clks1/2 = clkp1/2 = 2mhz (clkmc, clkpll and clksc stopped) +25?c 0.8 1.4 ma +125?c 1.3 2.9 (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol condition (at t a ) value remarks typ max unit preliminary mb96390 series fme-mb96390 rev 3 61 power supply cur- rent in sleep modes* i ccsrcl rc sleep mode with clks1/2 = clkp1/2 = 100khz, smcr:lpmss = 0 (clkmc, clkpll and clksc stopped. voltage regulator in high power mode) +25?c 0.3 0.5 ma +125?c 0.7 2 rc sleep mode with clks1/2 = clkp1/2 = 100khz, smcr:lpmss = 1 (clkmc, clkpll and clksc stopped. voltage regulator in low power mode) +25?c 0.05 0.15 ma +125?c 0.44 1.6 i ccssub sub sleep mode with clks1/2 = clkp1/2 = 32khz (clkmc, clkpll and clkrc stopped) +25?c 0.04 0.12 ma +125?c 0.43 1.55 power supply cur- rent in timer modes* i cctpll pll timer mode with clkmc = 4mhz, clkpll = 48mhz (clkrc and clksc stopped. core voltage at 1.9v) +25?c 1.5 2 ma +125?c 2 3.6 i cctmain main timer mode with clkmc = 4mhz, smcr:lpmss = 0 (clkpll, clkrc and clksc stopped. voltage regulator in high power mode) +25?c 0.35 0.55 ma +125?c 0.75 2 main timer mode with clkmc = 4mhz, smcr:lpmss = 1 (clkpll, clkrc and clksc stopped. voltage regulator in low power mode) +25?c 0.1 0.18 +125?c 0.5 1.6 (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol condition (at t a ) value remarks typ max unit preliminary mb96390 series 62 fme-mb96390 rev 3 power supply cur- rent in timer modes* i cctrch rc timer mode with clkrc = 2mhz, smcr:lpmss = 0 (clkmc, clkpll and clksc stopped. voltage regulator in high power mode) +25?c 0.35 0.5 ma +125?c 0.75 2 rc timer mode with clkrc = 2mhz, smcr:lpmss = 1 (clkmc, clkpll and clksc stopped. voltage regulator in low power mode) +25?c 0.07 0.15 ma +125?c 0.46 1.6 i cctrcl rc timer mode with clkrc = 100khz, smcr:lpmss = 0 (clkmc, clkpll and clksc stopped. voltage regulator in high power mode) +25?c 0.3 0.45 ma +125?c 0.65 1.9 rc timer mode with clkrc = 100khz, smcr:lpmss = 1 (clkmc, clkpll and clksc stopped. voltage regulator in low power mode) +25?c 0.03 0.1 ma +125?c 0.41 1.55 i cctsub sub timer mode with clksc = 32khz (clkmc, clkpll and clkrc stopped) +25?c 0.035 0.1 ma +125?c 0.42 1.55 power supply cur- rent in stop mode i cch vrcr:lpmb[2:0] = 110 b (core voltage at 1.8v) +25?c 0.02 0.08 ma +125?c 0.4 1.5 vrcr:lpmb[2:0] = 000 b (core voltage at 1.2v) +25?c 0.015 0.06 ma +125?c 0.3 1.2 power supply cur- rent for active low voltage detector i cclvd low voltage detector en- abled (rcr:lvde = 1) +25?c 90 140 a this current must be added to all power supply currents above +125?c 100 150 power supply cur- rent for active clock modulator i ccclomo clock modulator enabled (cmcr:pdx = 1) - 3 4.5 ma must be added to all current above (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol condition (at t a ) value remarks typ max unit preliminary mb96390 series fme-mb96390 rev 3 63 flash write/erase current i ccflash current for one flash module -1540ma must be added to all current above input capacitance c in - 15 30 pf high current outputs input capacitance c in --515pf other than c, av cc , av ss , avrh, avrl, v cc , v ss , dv cc , dv ss , high current outputs * the power supply current is measured with a 4mhz external clock connected to the main oscillator and a 32khz external clock connected to the sub oscillator. see chapter ?tandby mode and voltage regulator control circuit of the hardware manual for further details about voltage regulator control. (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol condition (at t a ) value remarks typ max unit preliminary mb96390 series 64 fme-mb96390 rev 3 4. ac characteristics source clock timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol pin value unit remarks min typ max clock frequency f c x0, x1 3 - 16 mhz when using a crystal oscillator, pll off 0 - 16 mhz when using an opposite phase external clock, pll off 3.5 - 16 mhz when using a crystal oscillator or oppo- site phase external clock, pll on clock frequency f fci x0 0 - 56 mhz when using a single phase external clock in fast clock input mode , pll off 3.5 - 56 mhz when using a single phase external clock in fast clock input mode , pll on clock frequency f cl x0a, x1a 32 32.768 100 khz when using an oscillation circuit 0 - 100 khz when using an opposite phase external clock x0a 0 - 50 khz when using a single phase external clock clock frequency f cr - 50 100 200 khz when using slow frequency of rc oscil- lator 1 2 4 mhz when using fast frequency of rc oscil- lator rc clock stabili- zation time t rcstab - 64 rc clock cycles applied after any reset and when acti- vating the rc oscillator. pll clock fre- quency f clkvco - 64 - 200 mhz permitted vco output frequency of pll (clkvco) pll phase jitter t pskew --- 5ns for clkmc (pll input clock) 4 mhz, jitter coming from external oscillator, crystal or resonator is not covered input clock pulse width p wh , p wl x0,x1 8 - - ns duty ratio is about 30% to 70% input clock pulse width p whl , p wll x0a,x1a 5 - - s preliminary mb96390 series fme-mb96390 rev 3 65 x0 t cyl p wh p wl v il v ih x0a t cyll p whl p wll v il v ih preliminary mb96390 series 66 fme-mb96390 rev 3 internal clock timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol core voltage settings unit remarks 1.8v 1.9v min max min max internal system clock fre- quency (clks1 and clks2) f clks1 , f clks2 0 92 0 96 mhz others than below 0 72 0 80 mhz mb96f395 internal cpu clock fre- quency (clkb), internal peripheral clock frequency (clkp1) f clkb , f clkp1 0 52 0 56 mhz others than below 0 36 0 40 mhz mb96f395 internal peripheral clock frequency (clkp2) f clkp2 028032mhz preliminary mb96390 series fme-mb96390 rev 3 67 external reset timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol pin value unit remarks min typ max reset input time t rstl rstx 500 - - ns 0.2 v cc rstx t rstl 0.2 v cc preliminary mb96390 series 68 fme-mb96390 rev 3 power on reset timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol pin value unit remarks min typ max power on rise time t r vcc 0.05 - 30 ms power off time t off vcc 1 - - ms 0.2 v t r 2.7v t off 0.2 v 0.2 v if the power supply is changed too rapidly, a power-on reset may occur. we recommend a smooth startup by restraining voltages when changing the power supply voltage during operation, as shown in the ?ure below. 3 v v cc v cc rising edge of 50 mv/ms maximum is allowed preliminary mb96390 series fme-mb96390 rev 3 69 external input timing note : relocated resource inputs have same characteristics (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol pin condition value unit used pin input func- tion min max input pulse width t inh t inl intn(_r) ? 200 ? ns external interrupt nmi(_r) nmi pnn_m 2*t clkp1 + 200 (t clkp1 =1/ f clkp1 ) ? ns general purpose io tinn(_r) reload timer ttgn(_r) ppg trigger input adtg(_r) ad converter trigger frckn(_r) free running timer external clock inn(_r) input capture v il v ih t inh v il v ih t inl external pin input preliminary mb96390 series 70 fme-mb96390 rev 3 slew rate high current outputs note : relocated resource inputs have same characteristics (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol pin condition value unit remarks min max output rise/fall time t r30 t f30 i/o circuit type m output driving strength set to ?0ma 15 ? ns v l v h v l v h t r30 t f30 slew rate output timing v h =v ol30 + 0.9 (v oh30 -v ol30 ) v l =v ol30 + 0.1 (v oh30 -v ol30 ) preliminary mb96390 series fme-mb96390 rev 3 71 usart timing warning: the values given below are for an i/o driving strength io drive = 5ma. if io drive is 2ma, all the maximum output timing described in the different tables must then be increased by 10ns. notes: ? ac characteristic in clk synchronized mode. ? c l is the load capacity value of pins when testing. ? depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. these parameters are shown in ?b96300 super series hardware manual ? t clkp1 is the cycle time of the peripheral clock 1 (clkp1), unit : ns *1: parameter n depends on t scyci and can be calculated as follows: if t scyci = 2*k*t clkp1 , then n = k, where k is an integer > 2 if t scyci = (2*k+1)*t clkp1 , then n = k+1, where k is an integer > 1 examples: (t a = -40?c to 125?c, v cc = 3.0v to 5.5v, v ss = av ss = 0v, io drive = 5ma, c l = 50pf) parameter symbol pin condition v cc =av cc = 4.5v to 5.5v v cc =av cc = 3.0v to 4.5v unit min max min max serial clock cycle time t scyci sckn internal shift clock mode 4 t clkp1 ? 4 t clkp1 ? ns sck sot delay time t slovi sckn, sotn -20 + 20 -30 + 30 ns sot sck delay time t ovshi sckn, sotn n*t clkp1 - 20 *1 ? n*t clkp1 - 30 *1 ? ns valid sin sck t ivshi sckn, sinn t clkp1 + 45 ? t clkp1 + 55 ? ns sck valid sin hold time t shixi sckn, sinn 0 ? 0 ? ns serial clock ??pulse width t slshe sckn external shift clock mode t clkp1 + 10 ? t clkp1 + 10 ? ns serial clock ??pulse width t shsle sckn t clkp1 + 10 ? t clkp1 + 10 ? ns sck sot delay time t slove sckn, sotn ? 2 t clkp1 + 45 ? 2 t clkp1 + 55 ns valid sin sck t ivshe sckn, sinn t clkp1 /2 + 10 ? t clkp1 /2 + 10 ? ns sck valid sin hold time t shixe sckn, sinn t clkp1 + 10 ? t clkp1 + 10 ? ns sck fall time t fe sckn ? 20 ? 20 ns sck rise time t re sckn ? 20 ? 20 ns t scyci n 4*t clkp1 2 5*t clkp1, 6*t clkp1 3 7*t clkp1, 8*t clkp1 4 ... ... preliminary mb96390 series 72 fme-mb96390 rev 3 internal shift clock mode sot t slovi sin v il v ih t ivshi v il v ih t shixi t ovshi sck for escr:sces = 0 0.8*v cc t scyci sck for escr:sces = 1 0.8*v cc 0.8*v cc 0.2*v cc 0.2*v cc 0.2*v cc 0.8*v cc 0.2*v cc external shift clock mode t fe v il v il v il v il sot t slove sin v il v ih t ivshe v il v ih t shixe v ih t re v ih t slshe v il v ih t shsle v ih v ih sck for escr:sces = 0 sck for escr:sces = 1 0.8*v cc 0.2*v cc preliminary mb96390 series fme-mb96390 rev 3 73 i 2 c timing *1 : for use at over 100 khz, set the peripheral clock 1 to at least 6 mhz. *2 : c b = capacitance of one bus line in pf. *3 : t clkp1 is the cycle time of the periperal clock clkp1. ? oh = 0.7 * v cc ? ol = 0.3 * v cc cmos hysteresis 0.7/0.3 input selected (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol standard-mode fast-mode* 1 unit min max min max scl clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition sda scl t hdsta 4.0 ? 0.6 ? s ??width of the scl clock t low 4.7 ? 1.3 ? s ??width of the scl clock t high 4.0 ? 0.6 ? s set-up time for a repeated start condition scl sda t susta 4.7 ? 0.6 ? s data hold time scl sda t hddat 0 3.45 0 0.9 s data set-up time sda scl t sudat 250 ? 100 ? ns set-up time for stop condition scl sda t susto 4.0 ? 0.6 ? s bus free time between a stop and start condition t bus 4.7 ? 1.3 ? s output fall time from 0.7*vcc to 0.3*vcc with a bus capacitance from 10 pf to 400 pf t of 20 + 0.1*c b * 2 250 20 + 0.1*c b * 2 250 ns capacitive load for each bus line c b ? 400 ? 400 pf pulse width of spikes which will be sup- pressed by input noise filter t sp n/a n/a 0 1*t clkp1 * 3 ns sda scl t low t sudat t hdsta t bus t hdsta t hddat t high t susta t susto preliminary mb96390 series 74 fme-mb96390 rev 3 5. analog digital converter note: the accuracy gets worse as |avrh - avrl| becomes smaller. (t a = -40 ?c to +125 ?c, 3.0 v avrh - avrl, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max resolution - - - - 10 bit total error - - - - 3 lsb nonlinearity error - - - - 2.5 lsb differential nonlinearity error -- - - 1.9 lsb zero transition voltage v ot ann avrl - 1.5 lsb avrl+ 0.5 lsb avrl + 2.5 lsb v full scale transition voltage v fst ann avrh - 3.5 lsb avrh - 1.5 lsb avrh + 0.5 lsb v compare time - - 1.0 - 16,500 s 4.5v v cc 5.5v 2.0 - - s 3.0v v cc < 4.5v sampling time - - 0.5 - - s 4.5v v cc 5.5v 1.2 - - s 3.0v v cc < 4.5v analog input leakage current (during conver- sion) i ain ann -1 - +1 a t a 105 ?c, av ss , avrl < v i < av cc , avrh -1.2 - +1.2 a 105 ?c < t a 125 ?c, av ss , avrl < v i < av cc , avrh analog input voltage range v ain ann avrl - avrh v reference voltage range avrh avrh 0.75 avcc - avcc v avrl avrl av ss - 0.25 av cc v power supply current i a avcc - 2.5 5 ma a/d converter active i ah avcc - - 5 a a/d converter not op- erated reference voltage cur- rent i r avrh/ avrl - 0.7 1 ma a/d converter active i rh avrh/ avrl --5 a a/d converter not op- erated offset between input channels - ann - - 4 lsb preliminary mb96390 series fme-mb96390 rev 3 75 definition of a/d converter terms resolution: analog variation that is recognized by an a/d converter. t otal error : difference between the actual value and the ideal value. the total error includes zero transition error, full-scale transition error and nonlinearity error. nonlinear ity error : deviation between a line across zero-transition line (?0 0000 0000 <--> ?0 0000 0001? and full-scale transition line (?1 1111 1110?<--> ?1 1111 1111? and actual conversion characteristics. diff erential nonlinear ity error : deviation of input voltage, which is required for changing output code by 1 lsb, from an ideal value. zero reading v oltage: input voltage which results in the minimum conversion value. full scale reading v oltage: input voltage which results in the maximum conversion value. 3ff 3fe 3fd 004 003 002 001 avrl avrh v nt 1.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} actual conversion characteristics (actually-measured value) actual conversion characteristics ideal characteristics digital output analog input total error of digital output ? = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb = (ideal value) avrh ? avrl 1024 [v] v ot (ideal value) = avrl + 0.5 lsb [v] v fst (ideal value) = avrh ? 1.5 lsb [v] v nt : a voltage at which digital output transitions from (n ? 1) to n. total error n: a/d converter digital output value preliminary mb96390 series 76 fme-mb96390 rev 3 3ff 3fe 3fd 004 003 002 001 avrl avrh avrl avrh n + 1 n n ? 1 n ? 2 v ot ( actual measurement value ) {1 lsb (n ? 1) + v ot } actual conversion characteristics v fst (actual measurement value) v nt (actual measurement value) actual conversion characteristics ideal characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output digital output analog input analog input v nt (actual measurement value) v (n + 1) t (actual measurement value) nonlinearity error differential nonlinearity error differential nonlinearity error of digital output n = 1 lsb = nonlinearity error of digital output n = v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] v ( n+1 ) t ? v nt 1 lsb ? 1 lsb [lsb] v fst ? v ot 1022 [v] n : a/d converter digital output value v ot : voltage at which digital output transits from ?00 h ?to ?01 h . v fst : voltage at which digital output transits from ?fe h ?to ?ff h . preliminary mb96390 series fme-mb96390 rev 3 77 accuracy and setting of the a/d converter sampling time if the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold capacitor is insuf?ient, adversely affecting the a/d conversion precision. to satisfy the a/d conversion precision, a suf?ient sampling time must be selected. the required sampling time depends on the external driving impedance r ext , the board capacitance of the a/d converter input pin c ext and the av cc voltage level. the following replacement model can be used for the calculation: the sampling time should be set to minimum ? ? the following approximation formula for the replacement model above can be used: t samp [min] = 7 (r ext (c ext + c in ) + (r ext + r adc ) c adc ) do not select a sampling time below the absolute minimum permitted value (0.5 s for 4.5v av cc 5.5v; 1.2 s for 3.0v av cc < 4.5v). if the sampling time cannot be suf?ient, connect a capacitor of about 0.1 f to the analog input pin. in this case the internal sampling capacitance c adc will be charged out of this external capacitance. a big external driving impedance also adversely affects the a/d conversion precision due to the pin input leakage current i il (static current before the sampling switch) or the analog input leakage current i ain (total leakage current of pin input and comparator during sampling). the effect of the pin input leakage current i il cannot be compensated by an external capacitor. the accuracy gets worse as |avrh - avrl| becomes smaller. comparator sampling switch r adc c adc analog r ext c ext input mcu source r ext : external driving impedance c ext : capacitance of pcb at a/d converter input r adc : resistance within mcu: 2.6k ? (max) for 4.5v av cc 5.5v 12k ? (max) for 3.0v av cc < 4.5v c adc : sampling capacitance within mcu: 10pf (max) c in c in : capacitance of mcu input pin: 15pf (max) preliminary mb96390 series 78 fme-mb96390 rev 3 6. alarm comparator (t a = -40 ?c to +125 ?c, v cc = av cc = 3.0v - 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max power supply current i a5almf av cc -2545 a alarm comparator enabled in fast mode (one channel) i a5alms -713 a alarm comparator enabled in slow mode (one channel) i a5almh --5 a alarm comparator disabled alarm pin input cur- rent i alin alarm0, alarm1 -1 - +1 at a = 25 ?c -3 - +3 at a = 125 ?c alarm pin input volt- age range v alin 0-av cc v external low threshold high->low transition v evtl(h->l) 0.36 * av cc -0.25 0.36 * av cc -0.1 -v intref = 0 external low threshold low->high transition v evtl(l->h) - 0.36 * av cc +0.1 0.36 * av cc +0.25 v external high threshold high->low transition v evth(h->l) 0.78 * av cc -0.25 0.78 * av cc -0.1 -v external high threshold low->high transition v evth(l->h) 0.78 * av cc +0.1 0.78 * av cc +0.25 v internal low threshold high->low transition v ivtl(h->l) 0.9 1.1 - v intref = 1 internal low threshold low->high transition v ivtl(l->h) - 1.3 1.55 v internal high threshold high->low transition v ivth(h->l) 2.2 2.4 - v internal high threshold low->high transition v ivth(l->h) - 2.6 2.85 v switching hysteresis v hys 50 - 300 mv comparison time t compf - 0.1 1 s cmd = 1 (fast) t comps -110 s cmd = 0 (slow) power-up stabilization time after enabling alarm comparator t pd - 1 10 ms threshold levels speci?d above are not guaranteed within this time slow/fast mode transi- tion time t cmd - 100 500 s preliminary mb96390 series fme-mb96390 rev 3 79 comparator output v xvtx(l->h) v hys v alin h l v xvtx(h->l) preliminary mb96390 series 80 fme-mb96390 rev 3 7. low voltage detector characteristics cilcr:lvl[3:0] are the low voltage detector level select bits of the cilcr register. for correct detection, the slope of the voltage level must satisfy . faster variations are regarded as noise and may not be detected. the functional operation of the mcu is guaranteed down to the minimum low voltage detection level of ?evel 0 (v dl0_min ). the electrical characteristics however are only valid in the speci?d range (usually down to 3.0v). (t a = -40 ?c to +125 ?c, v cc = av cc = 3.0v - 5.5v, v ss = av ss = 0v) parameter symbol value unit remarks min max stabilization time t lvdstab -75 s after power-up or change of detection level level 0 v dl0 2.7 2.9 v cilcr:lvl[3:0]=?000 level 1 v dl1 2.9 3.1 v cilcr:lvl[3:0]=?001 level 2 v dl2 3.1 3.3 v cilcr:lvl[3:0]=?010 level 3 v dl3 3.5 3.75 v cilcr:lvl[3:0]=?011 level 4 v dl4 3.6 3.85 v cilcr:lvl[3:0]=?100 level 5 v dl5 3.7 3.95 v cilcr:lvl[3:0]=?101 level 6 v dl6 3.8 4.05 v cilcr:lvl[3:0]=?110 level 7 v dl7 3.9 4.15 v cilcr:lvl[3:0]=?111 level 8 v dl8 4.0 4.25 v cilcr:lvl[3:0]=?000 level 9 v dl9 4.1 4.35 v cilcr:lvl[3:0]=?001 level 10 v dl10 not used level 11 v dl11 not used level 12 v dl12 not used level 13 v dl13 not used level 14 v dl14 not used level 15 v dl15 not used t d d v 0.004 v s ----- preliminary mb96390 series fme-mb96390 rev 3 81 low voltage detector operation in the following ?ure, the occurrence of a low voltage condition is illustrated. for a detailed description of the reset and startup behavior, please refer to the corresponding hardware manual chapter. voltage [v] time [s] v cc v dlx, min v dlx, max dv dt low voltage reset assertion normal operation power reset extension time preliminary mb96390 series 82 fme-mb96390 rev 3 8. flash memory program/erase characteristics *1: this value was converted from the results of evaluating the reliability of the technology (using arrhenius equation to convert high temperature measurements into normalized value at 85 o c) (t a = -40?c to 105?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter value unit remarks min typ max sector erase time - 0.9 3.6 s without erasure pre-program- ming time chip erase time - n*0.9 n*3.6 s without erasure pre-program- ming time (n is the number of flash sector of the device) word (16-bit width) programming time - 23 370 us without overhead time for sub- mitting write command program/erase cycle 10 000 - - cycle flash data retention time 20 - - year *1 preliminary mb96390 series fme-mb96390 rev 3 83 preliminary mb96390 series 84 fme-mb96390 rev 3 example characteristics 1. temperature dependency of power supply currents the following diagrams show the current consumption of samples with typical wafer process parameters in differ- ent operation modes. common condition for all operation modes: ? cc = av cc = 5.0v main clock = 4mhz external clock sub clock = 32khz external clock operation mode details: mode name details pll run 40 pll run mode current i ccpll with the following settings: ? clks1 = f clks2 = 80mhz ? clkb = f clkp1 = 40mhz ? clkp2 = 20mhz regulator in high power mode core voltage at 1.9v (vrcr:hpm[1:0] = 11 b ) 1 flash/rom wait states (mtcra=6b09 h ) rc oscillator and sub oscillator stopped pll run 24 pll run mode current i ccpll with the following settings: ? clks1 = f clks2 = 48mhz ? clkb = f clkp1 = f clkp2 = 24mhz regulator in high power mode core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) 0 flash/rom wait states (mtcra=2208 h ) rc oscillator and sub oscillator stopped main run main run mode current i ccmain with the following settings: ? clks1 = f clks2 = f clkb = f clkp1 = f clkp2 = 4mhz regulator in high power mode core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) 1 flash/rom wait states (mtcra=0239 h ) pll, rc oscillator and sub oscillator stopped rc run 2m rc run mode current i ccrch with the following settings: rc oscillator set to 2mhz (ckfcr:rcfs = 1) ? clks1 = f clks2 = f clkb = f clkp1 = f clkp2 = 2mhz regulator in high power mode core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) 1 flash/rom wait states (mtcra=0239 h ) pll, main oscillator and sub oscillator stopped preliminary mb96390 series fme-mb96390 rev 3 85 rc run 100k rc run mode current i ccrcl with the following settings: rc oscillator set to 100khz (ckfcr:rcfs = 0) ? clks1 = f clks2 = f clkb = f clkp1 = f clkp2 = 100khz regulator in low power mode a (smcr:lpms = 1) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) 1 flash/rom wait states (mtcra=0239 h ) pll, main oscillator and sub oscillator stopped sub run sub run mode current i ccsub with the following settings: ? clks1 = f clks2 = f clkb = f clkp1 = f clkp2 = 32khz regulator in low power mode a (by hardware) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) 1 flash/rom wait states (mtcra=0239 h ) pll, rc oscillator and main oscillator stopped pll sleep 40 pll sleep mode current i ccspll with the following settings: ? clks1 = f clks2 = 80mhz ? clkp1 = 40mhz ? clkp2 = 20mhz regulator in high power mode core voltage at 1.9v (vrcr:hpm[1:0] = 11 b ) rc oscillator and sub oscillator stopped pll sleep 24 pll sleep mode current i ccspll with the following settings: ? clks1 = f clks2 = 48mhz ? clkp1 = f clkp2 = 24mhz regulator in high power mode core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) rc oscillator and sub oscillator stopped main sleep main sleep mode current i ccsmain with the following settings: ? clks1 = f clks2 = f clkp1 = f clkp2 = 4mhz regulator in high power mode core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) pll, rc oscillator and sub oscillator stopped rc sleep 2m rc sleep mode current i ccsrch with the following settings: rc oscillator set to 2mhz (ckfcr:rcfs = 1) ? clks1 = f clks2 = f clkp1 = f clkp2 = 2mhz regulator in high power mode core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) pll, main oscillator and sub oscillator stopped rc sleep 100k rc sleep mode current i ccsrcl with the following settings: rc oscillator set to 100khz (ckfcr:rcfs = 0) ? clks1 = f clks2 = f clkp1 = f clkp2 = 100khz regulator in low power mode a (smcr:lpmss = 1) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) pll, main oscillator and sub oscillator stopped mode name details preliminary mb96390 series 86 fme-mb96390 rev 3 sub sleep sub sleep mode current i ccssub with the following settings: ? clks1 = f clks2 = f clkp1 = f clkp2 = 32khz regulator in low power mode a (by hardware) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) pll, rc oscillator and main oscillator stopped pll timer 48 pll timer mode current i cctpll with the following settings: ? clks1 = f clks2 = 48mhz regulator in high power mode core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) rc oscillator and sub oscillator stopped main timer main timer mode current i cctmain with the following settings: ? clks1 = f clks2 = 4mhz regulator in low power mode a (smcr:lpmss = 1) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) pll, rc oscillator and sub oscillator stopped rc timer 2m rc timer mode current i cctrch with the following settings: rc oscillator set to 2mhz (ckfcr:rcfs = 1) ? clks1 = f clks2 = 2mhz regulator in low power mode a (smcr:lpmss = 1) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) pll, main oscillator and sub oscillator stopped rc timer 100k rc timer mode current i cctrcl with the following settings: rc oscillator set to 100khz (ckfcr:rcfs = 0) ? clks1 = f clks2 = 100khz regulator in low power mode a (smcr:lpmss = 1) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) pll, main oscillator and sub oscillator stopped sub timer sub timer mode current i cctsub with the following settings: ? clks1 = f clks2 = 32khz regulator in low power mode a (by hardware) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) pll, rc oscillator and main oscillator stopped stop 1.8v stop mode current i cch with the following settings: regulator in low power mode b (by hardware) core voltage at 1.8v (vrcr:lpmb[2:0] = 110 b ) stop 1.2v stop mode current i cch with the following settings: regulator in low power mode b (by hardware) core voltage at 1.2v (vrcr:lpmb[2:0] = 000 b ) mode name details preliminary mb96390 series fme-mb96390 rev 3 87 mb96f395 pll run and sleep mode currents mb96f395 operation modes with medium currents 0 10 20 30 40 -60 -40 -20 0 20 40 60 80 100 120 ta [?c] icc[ma] pll sleep 24 pll sleep 40 pll run 24 pll run 40 0 1 2 3 4 5 -60 -40 -20 0 20 40 60 80 100 120 ta [?c] icc[ma] rc sleep 2m main sleep pll timer 48 rc run 2m main run preliminary mb96390 series 88 fme-mb96390 rev 3 mb96f395 low power mode currents 0.001 0.01 0.1 1 -60 -40 -20 0 20 40 60 80 100 120 ta [?c] icc[ma] stop 1.2v stop 1.8v rc timer 100k sub timer sub sleep sub rc sleep 100k rc timer 2m rc run 100k main timer preliminary mb96390 series fme-mb96390 rev 3 89 2. frequency dependency of power supply currents in pll run mode the following diagrams show the current consumption of samples with typical wafer process parameters in pll run mode at different frequencies and flash timing settings. measurement conditions: ? cc = av cc = 5.0v ta = 25?c ? clks1 = f clkb or f clks1 = 2*f clkb as described in diagram ? clks2 = f clks1 ? clkp1 = f clkb ? clkp2 = f clkb /2 core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) or 1.9v (vrcr:hpm[1:0] = 11 b ) as described in diagram main clock = 4mhz external clock flash memory timing settings: mtcra=2128 h /2208 h (0 flash wait states, f clks1 = 2*f clkb ) mtcra=0239 h /2129 h (1 flash wait state, f clks1 = f clkb ) mtcra=4c09 h /6b09 h (1 flash wait state, f clks1 = 2*f clkb ) mtcra=233a h (2 flash wait states, f clks1 = f clkb ) average flash access rate (number of read accesses to the flash per clkb clock cycle, no buffer hit): 0 flash wait states: 0.5 1 flash wait states: 0.33 2 flash wait states: 0.25 mb96f395 pll run mode currents 0 5 10 15 20 25 30 35 40 0 4 8 1216202428323640 clkb/clkp1 (mhz) iccpll (ma) 1 flash wait state (clks1=2*clkb, 1.9v) 1 flash wait state (clks1=2*clkb, 1.8v) 0 flash wait states (clks1=2*clkb, 1.8v) 1 flash wait state (clks1=clkb, 1.8v) 2 flash wait states (clks1=clkb, 1.8v) 2 flash wait states (clks1=clkb, 1.9v) : specified in "dc characteristics" preliminary mb96390 series 90 fme-mb96390 rev 3 package dimension mb96f39x lqfp 100p please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ 100-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 14.0 mm 14.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm m a x weight 0.65 g code (reference) p-lfqfp100-14 14-0.50 100-pin pl as tic lqfp (fpt-100p-m20) (fpt-100p-m20) c 2005 fujit s u limited f1000 3 1 s -c-2-1 14.00 0.10(.551 .004) s q 16.00?.20(.6 3 0 .00 8 ) s q 1 25 26 51 76 50 75 100 0.50(.020) 0.20 0.05 (.00 8 .002) m 0.0 8 (.00 3 ) 0.145 0.055 (.0057 .0022) 0.0 8 (.00 3 ) "a" index .059 .004 +.00 8 0.10 +0.20 1.50 (mo u nting height) 0 ? ~ 8 ? (0.50(.020)) (.024 .006) 0.60 0.15 0.25(.010) 0.10 0.10 (.004 .004) det a il s of "a" p a rt ( s t a nd off) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s ?005-200 8 fujit s u microelectronic s limited f1000 3 1 s -c-2-2 note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder. preliminary mb96390 series fme-mb96390 rev 3 91 ordering information *1: these devices are under development and speci?ation is preliminary. these products under development may change its speci?ation without notice. this datasheet is also valid for the following outdated devices: mb96f395ysa, mb96f395rsa, mb96f395ywa, mb96f395rwa. part number flash/rom subclock persistent low volt- age reset package mb96f395ysb pmc-gse2 *1 flash a (160kb) no yes 100 pin plastic lqfp (fpt-100p-m20) mb96f395rsb pmc-gse2 *1 no mb96f395ywb pmc-gse2 *1 yes yes mb96f395rwb pmc-gse2 *1 no mb96v300brb-es (for evaluation) emulated by ext. ram yes no 416 pin plastic bga (bga-416p-m02) preliminary mb96390 series 92 fme-mb96390 rev 3 revision history revision date modi?ation prelim 1 2008-04-18 initial draft prelim 2 2009-01-09 format adjusted to of?ial fujitsu microelectronics datasheet standard (mainly style changes and of?ial notes and disclaimer added) speci?d ad converter channel offset to 4lsb package code of mb96v300 corrected in ordering information internal lcd divider resistance value corrected: typ 35kohm -> 40kohm, max 50kohm -> 65kohm added voltage condition to pull-up resistance and lcd divide resistance spec ordering information: column ?lash/rom added, column ?emarks removed of?ial package dimension drawing with additional notes added empty pages removed alarm comparator: power supply current max values increased, comparison time reduced, mode transition time and power-up stabilization time newly added handling devices: notes added about serial communication and about using ceramic resonators. feature list and ac characteristics: 16mhz maximum frequency is valid for crys- tal oscillators. for resonators, maximum frequency depends on q-factor ac characteristics: pll phase skew spec added, clkvco min=64mhz vol3 spec improved: spec valid for 3ma load for full vcc range all icc (run/sleep/timer/stop mode) currents adjusted to evaluation results io map cleaned up (removed not available resources) absolute maximum ratings: pd spec corrected c-pin cap spec updated: 4.7uf-10uf capacitor with tolerance permitted preliminary mb96390 series fme-mb96390 rev 3 93 prelim 3 2010-06-25 ad converter i ain spec improved: 1ua valid up to 105deg, 1.2ua above 105deg note added that pll phase jitter spec does not include jitter coming from main clock alarm comparator: maximum power-up stabilization time increased to 10ms note added in dc characteristics how to select driving strength of ports i2c ac spec updated: tof, cb and tsp spec added, wrong footnotes and condition removed i/o circuit type: note added for type ? (slew rate control according to i2c spec) updated power supply current spec in run/sleep/timer/stop modes (new spec items in pll run/sleep mode, small adjustment of most other values) prepared example characteristics package dimension: added the following sentence under the ?ure: ?lease con?m the latest package dimension by following url. http://edevice.fujitsu.com/package/en-search/ ad converter: impact of input pin capacitance and external capacitance added to formula for calculation of the sampling time added speci?ation of rc clock stabilization time feature description i2c: ?-bit addressing?corrected to ?-bit addressing feature description ppg: ?eload timer over?w as clock input corrected to ?eload timer under?w as clock input company name updated on the cover page: fujitsu microelectronics limited -> fujitsu semiconductor limited ordering information: mb96f395**a -> mb96f395**b revision date modi?ation preliminary mb96390 series fme-mb96390 rev 3 preliminary mb96390 series fme-mb96390 rev 3 95 preliminary mb96390 series 96 fme-mb96390 rev 3 fujitsu semiconductor limited nomura fudosan shin-yokohama bldg. 10-23, shin-yokohama 2-chome, kohoku-ku yokohama kanagawa 222-0033, japan tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia paci? fujitsu microelectronics asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fmal.fujitsu.com/ fujitsu microelectronics shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectronics pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu semiconductor does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu semiconductor assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu semiconductor or any third party or does fujitsu semiconductor warrant non-infringement of any third-party's intellectual property right or other right by using such information. fujitsu semiconductor assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu semiconductor will not be liable against you and/or any third party for any claims or damages aris- ing in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over- current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department |
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